公开(公告)号：US20160035843A1

公开(公告)日：2016-02-04

申请号：US14782190

申请日：2013-04-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERIGES ALTERNATIVES ,  STMICROELECTRONICS INC

Inventor： Maud VINET ,  Laurent GRENOUILLET ,  Qing LIU

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/06 ,  H01L21/32 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L29/41783 ,  H01L21/31133 ,  H01L21/32 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/6656

Abstract: A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.

Abstract translation: 一种用于制造具有不同类型的具有升高的源极和漏极区域以及不同重叠区域的晶体管的微电子器件的方法。

公开(公告)号：US20160035820A1

公开(公告)日：2016-02-04

申请号：US14447678

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives ,  GLOBALFOUNDRIES Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

公开(公告)号：US09246458B2

公开(公告)日：2016-01-26

申请号：US14296914

申请日：2014-06-05

Applicant: STMicroelectronics, Inc.

Inventor： Davy Choi

IPC: H03G1/00 ,  H03F3/45 ,  H03F1/02

CPC classification number: H03G3/02 ,  H03F1/0205 ,  H03F1/26 ,  H03F3/3022 ,  H03F3/393 ,  H03F3/45 ,  H03F3/45094 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45336 ,  H03G1/0035 ,  H03G1/02 ,  H03G3/3036 ,  H03M1/18

Abstract: An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.

Abstract translation: 仪表放大器包括用于增益设定的第一和第二电阻器。 仪表放大器内的运算放大器包括耦合到放大器输出的有选择地使能的电流驱动源。 第一和第二电阻具有可变电阻。 控制电路被配置为选择第一和第二电阻器的可变电阻以实现仪器放大器的固定增益，并且进一步选择性地启用当前的驱动源。 控制电路接收下游可编程增益的指示（例如，从下游可编程增益放大器）。 第一和第二电阻器的可变电阻被选择为相对于下游可编程增益反相缩放，并且当前驱动源相对于下游可编程增益成比例地启用。

公开(公告)号：US09244236B2

公开(公告)日：2016-01-26

申请号：US14802504

申请日：2015-07-17

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: G02B6/42 ,  G02B6/43 ,  G02B6/122 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/12

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/124 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B6/4214 ,  G02B2006/12102

Abstract: A photonic integrated circuit includes optical circuitry fabricated over an underlying circuitry layer. The optical circuitry includes a dielectric material having recesses disposed within, layers of a light waveguide material deposited within the recesses, and lenses disposed over each layer of waveguide material. The underlying circuitry layer may include, for example, a semiconductor wafer as well as circuitry fabricated during front end of line (FEOL) semiconductor manufacturing such as, for example, sources, gates, drains, interconnects, contacts, resistors, and other circuitry that may be manufactured during FEOL processes. The underlying circuitry layer may also include circuitry manufactured during back end of line semiconductor manufacturing processes such as, for example, interconnect structures, metallization layers, and contacts.

Abstract translation: 光子集成电路包括在底层电路层上制造的光电路。 光学电路包括具有设置在沉积在凹部内的光波导材料的层内的凹槽的介电材料和设置在每层波导材料上的透镜。 底层电路层可以包括例如半导体晶片以及在前端（FEOL）半导体制造期间制造的电路，例如源，栅极，漏极，互连，触点，电阻器和其他电路，其中 可以在FEOL过程中制造。 底层电路层还可以包括在线半导体制造工艺的后端制造的电路，例如互连结构，金属化层和触点。

公开(公告)号：US09240466B2

公开(公告)日：2016-01-19

申请号：US14451174

申请日：2014-08-04

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Denis Rideau ,  Olivier Nier

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L29/66772 ,  H01L21/0217 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/785

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract translation: 本公开涉及一种对半导体层施加应力的方法，包括：在绝缘体上的结构上形成绝缘体结构，该绝缘体上硅结构具有与绝缘层相接触的半导体层，一个或多个与晶体管沟道所在半导体层的第一区对准的应力块 形成，其中所述应力块被应力，使得它们局部应力所述半导体层; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。

公开(公告)号：US09236909B2

公开(公告)日：2016-01-12

申请号：US14559756

申请日：2014-12-03

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov

IPC: H04L25/00 ,  H04B3/54 ,  H04L12/10 ,  H04L12/28

CPC classification number: H04L12/10 ,  G06F1/3209 ,  G06F1/3287 ,  H04B3/542 ,  H04L12/2838 ,  H04L2012/2843 ,  Y02D10/171

Abstract: An embodiment is an integrated System on Chip (SoC) including a communication interface configured to implement a communication protocol including functional blocks that are energized or de-energized individually so that a minimum power consumption is used to receive and detect a signal, and a receiver identification (ID) detection function configured to determine whether the signal is intended for the device in which the SoC resides. The SoC further includes a power management function configured to control which functions in the SoC and/or device in which the SoC resides are energized or de-energized depending on the results of the receiver ID detection function, and a power source capable of energizing a minimum number of the functional blocks required to receive and detect a signal, wherein the power source can be used in a low power state and switched over to a main power supply when the SoC is energized.

Abstract translation: 一个实施例是集成片上系统（SoC），其包括通信接口，该通信接口被配置为实现包括被单独通电或断电的功能块的通信协议，以便使用最小功耗来接收和检测信号，以及接收器 识别（ID）检测功能，被配置为确定信号是否适用于SoC驻留的设备。 SoC还包括功率管理功能，其被配置为根据接收机ID检测功能的结果来控制SoC驻留的SoC和/或设备中的哪些功能被激励或断电，以及能够激励 接收和检测信号所需的功能块的最小数量，其中当SoC被通电时，电源可以以低功率状态使用并切换到主电源。

公开(公告)号：US09232469B2

公开(公告)日：2016-01-05

申请号：US14025456

申请日：2013-09-12

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: G08C17/00 ,  H04W52/02

CPC classification number: H04W52/0209 ,  H04W52/0219 ,  Y02D70/142

Abstract: An additional cyclic redundancy check (CRC) is inserted in IEEE 802.11 beacon or data frames prior to the end of the frame, at a location following information sufficient for the receiving station to determine whether the frame is from an overlapping basic service set or intended for a different station and to extract other necessary or useful information such as a time of the next full beacon. Upon detecting the CRC, the receiving STA can terminate reception of the frame early to conserve power, and then enter a low power operational mode to further conserve power.

Abstract translation: 在足以使接收站确定帧是否来自重叠的基本业务集或旨在为重叠的基本业务集合的信息之后的位置处，在帧的结尾之前的IEEE 802.11信标或数据帧中插入附加的循环冗余校验（CRC） 一个不同的站，并提取其他必要或有用的信息，如下一个完整信标的时间。 在检测到CRC时，接收STA可以提前终止帧的接收以节省功率，然后进入低功率操作模式以进一步节省功率。

公开(公告)号：US20150380258A1

公开(公告)日：2015-12-31

申请号：US14314384

申请日：2014-06-25

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L21/308 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming fin structures whilst controlling the height of the fin structures with high uniformity across large areas are described. According to some aspects, a multi-layer structure comprising a first etch-stop layer and a second etch-stop layer separated from a substrate and from each other by spacer layers is formed on a substrate. Trenches may be formed through the first and second etch-stop layers. A buffer layer may be formed in the trenches, filling the trenches to a level approximately at a position of the first etch-stop layer. A semiconductor layer may be formed above the buffer layer and etched back to the second etch-stop layer to form semiconductor fins of highly uniform heights.

Abstract translation: 描述了形成翅片结构的方法和结构，同时在大面积上以高均匀性控制翅片结构的高度。 根据一些方面，在衬底上形成包括由衬底分离并通过间隔层彼此分离的第一蚀刻停止层和第二蚀刻停止层的多层结构。 沟槽可以通过第一和第二蚀刻停止层形成。 可以在沟槽中形成缓冲层，将沟槽填充到大致在第一蚀刻停止层的位置处的水平。 半导体层可以形成在缓冲层的上方并被回蚀刻到第二蚀刻停止层以形成高均匀高度的半导体鳍片。

公开(公告)号：US20150367373A1

公开(公告)日：2015-12-24

申请号：US14310886

申请日：2014-06-20

Applicant: STMicroelectronics, Inc.

Inventor： Simon Dodd ,  Joe Scheffelin ,  Dave Hunt ,  Matt Giere ,  Dana Gruenbacher ,  Faiz Sherman

IPC: B05B17/06 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02

CPC classification number: B05B17/0607 ,  B05B17/0638 ,  B05B17/0684 ,  B41J2/14016 ,  B41J2/14024 ,  B41J2/14056 ,  B41J2/14072 ,  B41J2/1433 ,  B41J2/1601 ,  B41J2/1632 ,  B41J2/175 ,  B41J2/17526 ,  B41J2/1753 ,  B41J2002/14338 ,  B41J2002/14491 ,  H05K1/0212 ,  H05K1/111 ,  H05K1/181 ,  Y10T29/49119

Abstract: The present disclosure is directed to a microfluidic die that includes a plurality of heaters above a substrate, a plurality of chambers and nozzles above the heaters, a plurality of first contacts coupled to the heaters, and a plurality of second contacts coupled to the heaters. The plurality of second contacts are coupled to each other and coupled to ground. The die includes a plurality of contact pads, a first signal line coupled to the plurality of second contacts and to a first one of the plurality of contact pads, and a plurality of second signal lines, each second signal line being coupled to one of the plurality of first contacts, groups of the second signal lines being coupled together to drive a group of the plurality of heaters with a single signal, each group of the second signal lines being coupled to a remaining one of the plurality of contact pads.

Abstract translation: 本公开涉及一种微流体管芯，其包括在基底上方的多个加热器，加热器上方的多个腔室和喷嘴，联接到加热器的多个第一触头以及耦合到加热器的多个第二触点。 多个第二触点彼此耦合并耦合到地。 芯片包括多个接触焊盘，耦合到多个第二触点和多个接触焊盘中的第一触点的第一信号线以及多个第二信号线，每个第二信号线耦合到 多个第一触点，第二信号线的组被耦合在一起以用单个信号驱动一组多个加热器，每组第二信号线耦合到多个接触垫中的剩余的一个。

公开(公告)号：US09219078B2

公开(公告)日：2015-12-22

申请号：US13865795

申请日：2013-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.

Abstract translation: 一种用于半导体制造的方法包括在包括至少一个硅锗（SiGe）沟道区的衬底上提供沟道区，所述衬底包括包括第一区和第二区的多个区域。 对于第一区域中的第一n型场效应晶体管（NFET）和第一p型场效应晶体管（PFET）以及第二区域中的第二NFET和第二PFET形成栅极结构， 第一PFET形成在SiGe沟道区上。 用于第一NFET的栅极结构包括具有第一功函数的栅极材料，并且用于第一PFET，第二NFET和第二PFET的栅极结构包括具有第二功函数的栅极材料，使得提供多阈值电压器件。