公开(公告)号：US07566946B2

公开(公告)日：2009-07-28

申请号：US11865432

申请日：2007-10-01

Applicant: Douglas D. Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

IPC: H01C10/00

CPC classification number: H01L27/0802 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.

Abstract translation: 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。

公开(公告)号：US20090155993A1

公开(公告)日：2009-06-18

申请号：US12348934

申请日：2009-01-06

Applicant: Douglas D. Coolbaugh ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L21/60

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552

Abstract: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

Abstract translation: 端子焊盘和制造端子焊盘的方法。 所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。 所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

公开(公告)号：US07491632B2

公开(公告)日：2009-02-17

申请号：US11164108

申请日：2005-11-10

Applicant: Douglas D. Coolbaugh ,  Xuefeng Liu ,  Robert M. Rassel ,  David C. Sheridan

Inventor： Douglas D. Coolbaugh ,  Xuefeng Liu ,  Robert M. Rassel ,  David C. Sheridan

IPC: H01L21/425

CPC classification number: H01L21/8249 ,  H01L29/0821 ,  H01L29/66272

Abstract: A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.

Abstract translation: 一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。 特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。 该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比） 。 本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。

公开(公告)号：US07397087B2

公开(公告)日：2008-07-08

申请号：US10710847

申请日：2004-08-06

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Vidhya Ramachandran ,  Robert M. Rassel

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Vidhya Ramachandran ,  Robert M. Rassel

IPC: H01L21/70

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L29/7833

Abstract: A FEOL/MEOL metal resistor that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure into a CMOS technology are provided.

Abstract translation: FEOL / MEOL金属电阻器具有紧密的薄层电阻公差（约5％或更低），高电流密度（约0.5 mA /微米或更大），比扩散电阻器更低的寄生效应和更低的TCR比 提供了标准的BEOL金属电阻器以及将这种金属电阻器结构集成到CMOS技术中的各种方法。

公开(公告)号：US20080158771A1

公开(公告)日：2008-07-03

申请号：US11616955

申请日：2006-12-28

Applicant: Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

Inventor： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

IPC: H01G4/30 ,  H01G9/00

CPC classification number: H01G4/33 ,  H01G4/005 ,  H01L23/5223 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/417 ,  H01L2924/00

Abstract: A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.

Abstract translation: 形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括在其中形成第一平面介质层和第一金属化层; 在其顶部形成第一钝化层; 在所述第一钝化层上形成平面导电层; 在指定区域中图案化和选择性地去除导电层直到第一钝化层以形成一组导电特征; 用高强度电介质涂层构图并保形地涂覆该组导电特征和暴露的第一钝化层; 在所述第一钝化层上设置第二电介质层并且包围所述一组导电特征; 图案化和选择性地去除第二衬底的部分以形成沟道和沟槽; 执行双镶嵌工艺以在沟槽和通道中形成第二金属化层，并在高强度电介质涂层上形成上导电表面。

公开(公告)号：US07394110B2

公开(公告)日：2008-07-01

申请号：US11307404

申请日：2006-02-06

Applicant: Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Kevin S. Petrarca ,  Anthony K. Stamper ,  Richard P. Volant

Inventor： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Kevin S. Petrarca ,  Anthony K. Stamper ,  Richard P. Volant

IPC: H01L23/62

CPC classification number: H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

Abstract translation: 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。

公开(公告)号：US07361993B2

公开(公告)日：2008-04-22

申请号：US10908346

申请日：2005-05-09

Applicant: Douglas D. Coolbaugh ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L29/40

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552

Abstract: Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.

Abstract translation: 端子焊盘和制造端子焊盘的方法。 所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。 所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

公开(公告)号：US20080087978A1

公开(公告)日：2008-04-17

申请号：US11548310

申请日：2006-10-11

Applicant: Douglas D. Coolbaugh ,  Xuefeng Liu ,  Robert M. Rassel ,  David C. Sheridan ,  Steven H. Voldman

Inventor： Douglas D. Coolbaugh ,  Xuefeng Liu ,  Robert M. Rassel ,  David C. Sheridan ,  Steven H. Voldman

IPC: H01L29/93 ,  H01L21/20

CPC classification number: H01L29/0821 ,  H01L21/743 ,  H01L21/8249 ,  H01L27/0251 ,  H01L29/66242 ,  H01L29/737 ,  H01L29/78

Abstract: A structure and method comprises a deep sub-collector located in a first epitaxial layer and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The device further comprises a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.

Abstract translation: 一种结构和方法包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区。 该器件还包括从器件的表面穿过第一和第二外延层到达深子集电极的通孔结构，以及从器件的表面穿透且围绕掺杂区域的沟槽隔离结构。

公开(公告)号：US07060612B2

公开(公告)日：2006-06-13

申请号：US10711130

申请日：2004-08-26

Applicant: Douglas D. Coolbaugh ,  Heidi L. Greer ,  Robert M. Rassel

Inventor： Douglas D. Coolbaugh ,  Heidi L. Greer ,  Robert M. Rassel

IPC: H01L21/44

CPC classification number: H01L21/2652 ,  H01C17/26 ,  H01C17/265 ,  H01L28/20

Abstract: A method of fabricating a resistor in which the resistance value of the resistor is measured and adjusted after silicidation is provided. The method of the present invention begins with first providing at least one resistor, e.g., polysilicon, having a resistance value on a surface of a semiconductor substrate. The at least one resistor has been subjected to a silicidation process. Next, the resistance value of the at least one resistor is measured to determine the actual resistance of the resistor after silicidation. After the measuring step, the resistance of the resistor is adjusted to achieve a desired resistance value. The adjusting may include a post silicidation rapid thermal anneal and/or a post silicidation ion implantation and a low temperature rapid thermal anneal step.

Abstract translation: 提供了在硅化后测量和调整电阻器的电阻值的电阻器的制造方法。 本发明的方法首先开始在半导体衬底的表面上提供具有电阻值的至少一个电阻器，例如多晶硅。 至少一个电阻器已进行硅化处理。 接下来，测量至少一个电阻器的电阻值，以确定硅化后电阻器的实际电阻。 在测量步骤之后，调整电阻器的电阻以获得所需的电阻值。 调整可以包括后硅化快速热退火和/或后硅化离子注入和低温快速热退火步骤。

公开(公告)号：US06984593B2

公开(公告)日：2006-01-10

申请号：US10653912

申请日：2003-09-04

Applicant: Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Steve S. Williams

Inventor： Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Steve S. Williams

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/31662 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/32055 ,  H01L29/66272 ,  Y10S438/981

Abstract: A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.

Abstract translation: 一种形成半导体器件的方法，所述半导体器件通过在小于约700℃的温度下快速热氧化衬底表面来处理衬底的表面以产生表面上材料的不连续生长。