利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

76 条记录 (耗时 0.038 秒)

    Passive circuits for de-multiplexing display inputs
    51.
    发明授权
    Passive circuits for de-multiplexing display inputs 有权
    无源电路用于解复用显示输入

    公开(公告)号：US07777715B2

    公开(公告)日：2010-08-17

    申请号：US11479865

    申请日：2006-06-29

    申请人： Clarence Chui ,  Alan Lewis ,  Marc M. Mignard

    发明人： Clarence Chui ,  Alan Lewis ,  Marc M. Mignard

    IPC分类号： G09G3/34 ,  G09G3/00 ,  G09G5/00 ,  G02B26/02

    CPC分类号： G09G3/3466 ,  G02B26/001 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2310/06 ,  G09G2330/021

    摘要： A display array which can reduce the row connections between the display and the driver circuit and methods of manufacturing and operating the same are disclosed. In one embodiment, a display device comprises an array of MEMS display elements and a plurality of voltage dividers coupled to the array and configured to provide row output voltages to drive the array, wherein each row is connected to at least two inputs joined by a voltage divider.

    摘要翻译： 公开了可以减少显示器和驱动电路之间的行连接的显示阵列及其制造和操作方法。 在一个实施例中，显示装置包括耦合到阵列的MEMS显示元件阵列和多个分压器，并被配置为提供行输出电压来驱动阵列，其中每一行连接到由电压连接的至少两个输入 分隔线

    MEMS device and interconnects for same
    54.
    发明申请
    MEMS device and interconnects for same 失效
    MEMS器件和互连相同

    公开(公告)号：US20070103028A1

    公开(公告)日：2007-05-10

    申请号：US11540485

    申请日：2006-09-29

    申请人： Alan Lewis ,  Manish Kothari ,  John Batey ,  Teruo Sasagawa ,  Ming-Hau Tung ,  Gregory U'Ren ,  Stephen Zee

    发明人： Alan Lewis ,  Manish Kothari ,  John Batey ,  Teruo Sasagawa ,  Ming-Hau Tung ,  Gregory U'Ren ,  Stephen Zee

    IPC分类号： H02N11/00

    CPC分类号： B81B7/0006 ,  B81B7/007 ,  B81B2201/047 ,  G02B26/001 ,  H02N1/006

    摘要： A microelectromechanical systems device having an electrical interconnect between circuitry outside the device and at least one of an electrode and a movable layer within the device. At least a portion of the electrical interconnect is formed from the same material as a conductive layer between the electrode and a mechanical layer of the device. In an embodiment, this conductive layer is a sacrificial layer that is subsequently removed to form a cavity between the electrode and the movable layer. The sacrificial layer is preferably formed of molybdenum, doped silicon, tungsten, or titanium. According to another embodiment, the conductive layer is a movable reflective layer that preferably comprises aluminum.

    摘要翻译： 一种微机电系统装置，其具有在所述装置外部的电路和所述装置内的电极和可移动​​层中的至少一个之间的电互连。 电互连的至少一部分由与电极和器件的机械层之间的导电层相同的材料形成。 在一个实施例中，该导电层是牺牲层，其随后被去除以在电极和可移动​​层之间形成空腔。 牺牲层优选由钼，掺杂硅，钨或钛形成。 根据另一实施例，导电层是优选包括铝的可移动反射层。

    Computer simulator for continuously variable transmissions
    55.
    发明申请
    Computer simulator for continuously variable transmissions 审中-公开
    用于无级变速器的计算机模拟器

    公开(公告)号：US20050192785A1

    公开(公告)日：2005-09-01

    申请号：US11063733

    申请日：2005-02-24

    申请人： Alan Lewis ,  Toshihiro Saito

    发明人： Alan Lewis ,  Toshihiro Saito

    IPC分类号： F16H9/12 ,  F16H9/18 ,  G06F17/50 ,  G06G7/48

    CPC分类号： G06F17/5009 ,  F16H9/18 ,  G06F17/5086 ,  G06F17/5095 ,  G06F2217/02

    摘要： Improvements are made to a multi-body simulation (MBS) for computing belt dynamics in metal pushing V-Belts for CVTs. All of the improvements combine to more accurately model the forces in the CVT mechanism, and also provide insight into the mechanism performance. One improvement more accurately captures effects of ring bending, using ring and block gap geometry to calculate bending forces and torques. A second improvement is implementation of a thrust controller to adjust pulley thrust to control CVT input/output speed ratio. Pulley thrust is adjusted by means of a feedback loop until a desired speed ratio is obtained. Finally, pulley conical (tilt) deflection is modeled using a stiffness representation that is a function of the block radius on the pulley face.

    摘要翻译： 对用于CVT的金属推动V型皮带计算皮带动力学的多体模拟（MBS）进行了改进。 所有的改进结合起来，更准确地模拟了CVT机制中的力量，并提供了机构性能的洞察。 一个改进更准确地捕获环弯曲的影响，使用环和块间隙几何来计算弯曲力和扭矩。 第二个改进是实施推力控制器来调节滑轮推力以控制CVT输入/输出速度比。 通过反馈回路调节滑轮推力，直到获得所需的速比。 最后，使用作为滑轮面上的块半径的函数的刚度表示来对滑轮锥形（倾斜）偏转进行建模。

    Humanized antibodies to CD38
    56.
    发明申请
    Humanized antibodies to CD38 审中-公开
    CD38人源化抗体

    公开(公告)号：US20050158305A1

    公开(公告)日：2005-07-21

    申请号：US10965585

    申请日：2004-10-14

    申请人： Jonathan Ellis ,  Alan Lewis

    发明人： Jonathan Ellis ,  Alan Lewis

    IPC分类号： C12N15/02 ,  A61K38/00 ,  A61K39/395 ,  A61P29/00 ,  A61P35/00 ,  A61P37/00 ,  C07K16/28 ,  C07K16/46 ,  C12P21/08 ,  C07K16/44 ,  C12N5/06

    CPC分类号： C07K16/2896 ,  A61K38/00 ,  C07K16/465 ,  C07K2317/24 ,  C07K2319/00

    摘要： The present invention relates to a monoclonal antibody, preferably, with specificity for CD38, having CDRs of foreign origin and a recipient framework region having a sequence of human or primate origin, wherein the original amino acid residues in position 29 and/or 78 of the sequence of the recipient framework region of the heavy chain is replaced by a replacement amino acid residue that is the same or similar to that in the corresponding position of the sequence of the corresponding framework region of the heavy chain of the antibody from which the CDRs are derived. Method of preparation of said antibody. Pharmaceutical composition containing said antibody. Use of said antibody for the treatment of cancer and autoimmune diseases.

    摘要翻译： 本发明涉及优选具有CD38特异性的单克隆抗体，其具有国外起源的CDR和具有人或灵长类来源序列的受体框架区，其中位于第29位和/或78位的原始氨基酸残基 重链的受体框架区的序列被替换的氨基酸残基取代，所述替换氨基酸残基与抗体重链的相应构架区的序列的相应位置相同或相似，其中CDR是 派生。 所述抗体的制备方法。 含有所述抗体的药物组合物。 使用所述抗体治疗癌症和自身免疫性疾病。

    Method of fabrication of a support structure for a semiconductor device
    57.
    发明申请
    Method of fabrication of a support structure for a semiconductor device 有权
    制造半导体器件的支撑结构的方法

    公开(公告)号：US20050014349A1

    公开(公告)日：2005-01-20

    申请号：US10735695

    申请日：2003-12-16

    申请人： Glen Carey ,  Ian Jenks ,  Alan Lewis ,  Rene Lujan ,  Hailong Zhou

    发明人： Glen Carey ,  Ian Jenks ,  Alan Lewis ,  Rene Lujan ,  Hailong Zhou

    IPC分类号： C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/36 ,  H01L33/00 ,  H01S5/02 ,  H01S5/183 ,  H01S5/323

    CPC分类号： H01S5/18305 ,  H01L21/02395 ,  H01L21/02543 ,  H01L21/02546 ,  H01L33/0079 ,  H01S5/0217 ,  H01S5/0224 ,  H01S5/141 ,  H01S5/323

    摘要： A method of fabricating a semiconductor device is described. In this method, a starting substrate of sufficient thickness is selected that has the required defect density levels, which may result in an undesirable doping level. Then a semiconductor layer having a desired doping level is formed on the starting substrate. The resulting semiconductor layer has the required defect density and doping levels for the final product application. After active components, electrical conductors, and any other needed structures are formed on the semiconductor layer, the starting substrate is removed leaving a desired thickness of the semiconductor layer. In a VECSEL application, the active components can be a gain cavity, where the semiconductor layer has the necessary defect density and doping levels to maximize wall plug efficiency (WPE). In one embodiment, the doping of the semiconductor layer is not uniform. For example, a majority of the layer is doped at a low level and the remainder is doped at a much higher level. This can result in improved WPE at particular thicknesses for the higher doped material.

    摘要翻译： 描述制造半导体器件的方法。 在该方法中，选择具有所需缺陷密度水平的足够厚度的起始衬底，这可能导致不期望的掺杂水平。 然后在起始衬底上形成具有期望的掺杂水平的半导体层。 所得到的半导体层具有所需的缺陷密度和最终产品应用的掺杂水平。 在有源部件之后，在半导体层上形成电导体和任何其它需要的结构，去除起始衬底，留出半导体层的所需厚度。 在VECSEL应用中，有源部件可以是增益腔，其中半导体层具有必要的缺陷密度和掺杂水平以最大化壁插拔效率（WPE）。 在一个实施例中，半导体层的掺杂不均匀。 例如，该层的大部分以低电平掺杂，其余部分以更高的水平掺杂。 这可以导致用于较高掺杂材料的特定厚度的改进的WPE。

    Integrated sample and hold circuit with feedback circuit to increase storage time
    59.
    发明授权
    Integrated sample and hold circuit with feedback circuit to increase storage time 失效
    集成样本和保留电路与反馈电路增加存储时间

    公开(公告)号：US5164616A

    公开(公告)日：1992-11-17

    申请号：US459096

    申请日：1989-12-29

    申请人： Alan Lewis ,  Richard H. Bruce ,  William F. Gunning

    发明人： Alan Lewis ,  Richard H. Bruce ,  William F. Gunning

    IPC分类号： G11C27/02

    CPC分类号： G11C27/024

    摘要： An integrated sample and hold circuit includes a capacitor that is charged through a channel, such as a first input transistor's channel. Feedback circuitry connected to the first transistor's channel leads maintains approximately zero voltage difference between the channel leads to prevent leakage current when the first transitor is turned off. Isolation circuitry, such as a second input transistor, isolates the first transistor from the input voltage while a voltage level is being stored, and the gates of both input transistors can be connected to receive the same store signal. The feedback circuitry can include a follower transistor with its gate connected to the first transistor's output lead and a first channel lead connected to the first transistor's input lead and to load circuitry that maintains current flow through the follower transistor. To ensure that it does not pass current to or from the capacitive element, the follower transistor can be an MOS device or other insulated gate transistor. The follower transistor's other channel lead can be connected to a bias voltage that, together with the current flow, keeps the follower transistor's gate and first channel lead at the stored voltage level. The load circuitry can include a transistor identical to the follower transistor, with one of its channel leads connected to the follower transistor's first channel lead and with its other channel lead and its gate lead connected to a bias voltage that maintains sufficient current flow through the follower transistor. The substrate can be an insulating material such as glass, quartz, sapphire, silicon dioxide, or silicon nitride, and the circuitry can be thin film structures, amorphous silicon, polysilicon, or single crystal devices, so that the only significant leakage path to and from the capacitive element is through the first input transistor's channel.