公开(公告)号：US20060118937A1

公开(公告)日：2006-06-08

申请号：US11291780

申请日：2005-12-02

申请人： Mitsuaki Katagiri ,  Atsushi Hiraishi ,  Fumiyuki Osanai

发明人： Mitsuaki Katagiri ,  Atsushi Hiraishi ,  Fumiyuki Osanai

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L25/105 ,  H01L2224/50 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311

摘要： Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.

摘要翻译： 与第一半导体芯片的第一信号传输路径中的第一路径部分的对应部分是互连部件和第二路径部分，到第二半导体芯片的第二信号传输路径，并且不形成在第一条带上。 允许第二信号传输路径的电长度独立于第一带被调整，使得第二信号传输路径的电长度可以容易地等于或基本等于第一信号传输路径的电长度。

公开(公告)号：US06046609A

公开(公告)日：2000-04-04

申请号：US188369

申请日：1998-11-10

申请人： Hiroshi Toyoshima ,  Masashige Harada ,  Tomohiro Nagano ,  Yoji Nishio ,  Atsushi Hiraishi ,  Kunihiro Komiyaji ,  Hideharu Yahata ,  Kenichi Fukui ,  Hirofumi Zushi ,  Takahiro Sonoda ,  Haruko Kawachino ,  Sadayuki Morita

发明人： Hiroshi Toyoshima ,  Masashige Harada ,  Tomohiro Nagano ,  Yoji Nishio ,  Atsushi Hiraishi ,  Kunihiro Komiyaji ,  Hideharu Yahata ,  Kenichi Fukui ,  Hirofumi Zushi ,  Takahiro Sonoda ,  Haruko Kawachino ,  Sadayuki Morita

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/409

CPC分类号： G11C7/065

摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

摘要翻译： 一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管 到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。 基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以降低输出响应的延迟时间。

公开(公告)号：US5963483A

公开(公告)日：1999-10-05

申请号：US133952

申请日：1998-08-14

申请人： Hideharu Yahata ,  Kenichi Fukui ,  Yoji Nishio ,  Atsushi Hiraishi ,  Sadayuki Morita

发明人： Hideharu Yahata ,  Kenichi Fukui ,  Yoji Nishio ,  Atsushi Hiraishi ,  Sadayuki Morita

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal. An output buffer receives and outputs the amplified output data signal from the output latch. Each latch includes a first latch for holding and outputting a data signal according to the clock signal, a first switch connected to the first latch for allowing a data signal to pass to the first latch according to the clock signal, and a second latch for holding and outputting a data signal according to the clock signal, and a second switch, connected between the first and second latches, for allowing a data signal to pass from the first latch to the second latch according to the clock signal.

摘要翻译： 一种同步存储单元，包括用于接收地址数据的多个输入缓冲器，用于根据时钟信号从输入缓冲器中保存和输出地址数据的多个输入锁存器，用于从输入端解码地址数据的多个解码器 锁存器和具有多个存储器单元的存储单元阵列，存储单元根据解码器解码的地址数据经由位线存储和输出数据信号。 还提供了用于放大位线上的输出数据信号的读出放大器，用于根据由解码器解码的地址数据来选择放大的输出数据信号之一的选择器，以及用于保存并输出放大的输出的选择器输出锁存器 来自选择器的数据信号根据时钟信号。 输出锁存器根据时钟信号保存并输出来自选择器输出锁存器的放大输出数据信号。 输出缓冲器从输出锁存器接收并输出放大的输出数据信号。 每个锁存器包括用于根据时钟信号保持和输出数据信号的第一锁存器，连接到第一锁存器的第一开关，用于根据时钟信号使数据信号传送到第一锁存器;以及第二锁存器，用于保持 并根据时钟信号输出数据信号，以及连接在第一和第二锁存器之间的第二开关，用于根据时钟信号允许数据信号从第一锁存器传递到第二锁存器。

公开(公告)号：US5731219A

公开(公告)日：1998-03-24

申请号：US458616

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L21/70

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current. A thickness of an oxide film formed on gate electrodes of the transfer MISFETs and word lines is thicker than an oxide film formed on gate electrodes of the drive MISFETs, so that data line pads can be formed in self-alignment with the oxide film and side wall spacers on the gate electrodes of the transfer MISFETs.

摘要翻译： 这里公开了一种半导体集成电路器件，其特征在于包括SRAM，其SRAM具有通过字线和驱动MISFET来控制的转移MISFET构成的存储单元，以及形成该器件的方法。 驱动MISFET的栅电极和存储单元的转移MISFET以及字线分别由不同的导电层形成。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 源极线由与字线的导电层相同的导电层形成。 在驱动MISFET的栅电极上形成抗氧化膜，以减少由这些栅电极的边缘部分的氧化引起的应力，并减少产生的漏电流。 形成在转移MISFET和字线的栅电极上的氧化膜的厚度比形成在驱动MISFET的栅电极上的氧化膜厚，使得数据线焊盘可以形成为与氧化膜和侧面自对准 传输MISFET的栅电极上的壁间隔物。

公开(公告)号：US5656836A

公开(公告)日：1997-08-12

申请号：US460129

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected-with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储单元的两个转移MISFET具有彼此间隔开并沿相同方向延伸的两个相应字线连接的各自的栅电极。 由两个字线限定的区域配置有两个驱动MISFET和源极线。

公开(公告)号：US5619151A

公开(公告)日：1997-04-08

申请号：US473742

申请日：1995-06-07

申请人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira ide ,  Masahiro Yamamura ,  Hideaki Uchida

发明人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira ide ,  Masahiro Yamamura ,  Hideaki Uchida

IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/0175 ,  H03K5/153 ,  G01R29/02 ,  H03K3/033

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/017518 ,  H03K5/1534

摘要： A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

摘要翻译： 一种半导体存储器件，包括以下中的至少一个：（1）响应于输入地址产生内部地址信号的输入缓冲器电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路 具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变 并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据响应于ATD信号的时钟发生器的信号来控制器件的解码器，读出放大器和输出缓冲器。

公开(公告)号：US5572480A

公开(公告)日：1996-11-05

申请号：US459961

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  G11C8/00

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。

公开(公告)号：US5544125A

公开(公告)日：1996-08-06

申请号：US383866

申请日：1995-02-06

申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  G11C8/00

CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

摘要翻译： 提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端 信号，并且每个都耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 还提供了一种改进的读/写布置，用于这样的半导体存储器电路，其包括在写入操作期间防止公共读取线与数据线连接的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

公开(公告)号：US5502820A

公开(公告)日：1996-03-26

申请号：US385656

申请日：1995-02-08

申请人： Atsushi Hiraishi ,  Takashi Akioka ,  Yutaka Kobayashi ,  Yuji Yokoyama ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Hideaki Uchida ,  Akira Ide

发明人： Atsushi Hiraishi ,  Takashi Akioka ,  Yutaka Kobayashi ,  Yuji Yokoyama ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Hideaki Uchida ,  Akira Ide

IPC分类号： G11C11/417 ,  G11C11/409 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/088 ,  H03K19/0944 ,  G06F13/00

CPC分类号： H03K19/09448 ,  H03K17/164 ,  H03K19/00361

摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.

摘要翻译： 提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。 缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。 这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。 例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。 电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

公开(公告)号：US5274594A

公开(公告)日：1993-12-28

申请号：US840819

申请日：1992-02-25

申请人： Kazumasa Yanagisawa ,  Atsushi Hiraishi ,  Hideyuki Aoki ,  Satoshi Oguchi ,  Sadayuki Ohkuma

发明人： Kazumasa Yanagisawa ,  Atsushi Hiraishi ,  Hideyuki Aoki ,  Satoshi Oguchi ,  Sadayuki Ohkuma

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C29/832 ,  G11C29/84

摘要： A static RAM comprises: column select circuits for connecting a plurality of pairs of corresponding complementary data lines at a unit of each pair with common complementary data lines; and redundant circuits each composed of the complementary data line pair and the column select circuit corresponding to the unit. Load MOSFETs of the complementary data lines are arranged close to the column select circuits to inhibit the column selecting operations by a decoder circuit and turn off the load MOSFETs when fuse means is cut. An access to a defective address is detected by a redundant decoder stored with the defective address, when the fuse means is selectively cut, to select the column select circuits of the redundant circuit.

摘要翻译： 静态RAM包括：列选择电路，用于以每对的单位将多对相应的互补数据线对与公共补充数据线连接; 以及各自由互补数据线对和与该单元对应的列选择电路组成的冗余电路。 互补数据线的负载MOSFET布置成靠近列选择电路，以禁止解码器电路的列选择操作，并且当熔断装置被切断时关断负载MOSFET。 当选择性地切断熔丝装置时，通过存储有缺陷地址的冗余解码器来检测缺陷地址，以选择冗余电路的列选择电路。