公开(公告)号：US10263013B2

公开(公告)日：2019-04-16

申请号：US15441711

申请日：2017-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/84 ,  H01L49/02 ,  H01L21/265 ,  H01L29/08 ,  H01L29/45 ,  H01L27/06 ,  H01L29/06

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

公开(公告)号：US20190074364A1

公开(公告)日：2019-03-07

申请号：US15693537

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laura J. Schutz ,  Anthony K. Stamper ,  Siva P. Adusumilli ,  Joshua F. Dillon

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/41758 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575

Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.

公开(公告)号：US10211090B2

公开(公告)日：2019-02-19

申请号：US15291561

申请日：2016-10-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/732 ,  H01L29/737 ,  H01L23/482 ,  H01L23/31

Abstract: Disclosed are embodiments of a transistor, which incorporates an airgap for low base-emitter capacitance (Cbe). Each embodiment of the transistor has a monocrystalline base and, within the monocrystalline base, an intrinsic base region and an extrinsic base region positioned laterally adjacent to the intrinsic base region, wherein the intrinsic and extrinsic base regions have co-planar top surfaces. An essentially T-shaped emitter in cross-section has a lower emitter region on the intrinsic base region and an upper emitter region above the lower emitter region. Each embodiment of the transistor further has an airgap, which is positioned laterally adjacent to the lower emitter region so as to be between the extrinsic base region and the upper emitter region. Thus, the entire airgap is above the co-planar top surfaces of the intrinsic base region and the extrinsic base region. Also disclosed herein are methods of forming the transistor embodiments.

公开(公告)号：US10192779B1

公开(公告)日：2019-01-29

申请号：US15935606

申请日：2018-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L27/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/02

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A non-single-crystal layer has a first section arranged beneath the trench isolation regions and a second section arranged beneath the active device region. The first section of the non-single-crystal layer has a first width in a vertical direction. The second section of the non-single-crystal layer has a second width in the vertical direction that is less than the first width of the first section of the non-single-crystal layer.

公开(公告)号：US10163673B2

公开(公告)日：2018-12-25

申请号：US14047237

申请日：2013-10-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Kenneth F. McAvey, Jr. ,  Charles F. Musante ,  Anthony K. Stamper

IPC: H01L21/673 ,  H01L21/683

Abstract: The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly, a method of temporarily bonding a semiconductor wafer to a wafer carrier with a multi-layered contact layer as well as a structure. A method is disclosed that includes: forming a first layer on a surface of a semiconductor wafer; forming a second layer on the first layer; bonding a perforated carrier to the second layer; and removing the semiconductor wafer from the perforated carrier. The first layer may be composed of an adhesive. The second layer may be composed of a material having a higher outgassing temperature than the first layer.

公开(公告)号：US20180166536A1

公开(公告)日：2018-06-14

申请号：US15372929

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/10 ,  H01L23/66 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/762 ,  H01L21/76283 ,  H01L21/764 ,  H01L21/823481 ,  H01L23/66 ,  H01L25/18 ,  H01L29/0649 ,  H01L29/78 ,  H01L2223/6683

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to active and passive radio frequency (RF) components with deep trench isolation structures and methods of manufacture. The structure includes a bulk high resistivity wafer with a deep trench isolation structure having a depth deeper than a maximum depletion depth at worst case voltage bias difference between devices which are formed on the bulk high resistivity wafer.

公开(公告)号：US09966182B2

公开(公告)日：2018-05-08

申请号：US14942311

申请日：2015-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Venkata Narayana Rao Vanukuru

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F21/12 ,  H01F41/041 ,  H01F2027/2809

Abstract: This disclosure relates generally to semiconductors, and more particularly, to structures and methods for implementing high performance multi-frequency inductors with airgaps or other low-k dielectric material. The structure includes: a plurality of concentric conductive bands; a low-k dielectric area selectively placed between inner windings of the plurality of concentric conductive bands; and insulator material with a higher-k dielectric material than the low-k dielectric area selectively placed between remaining windings of the plurality of concentric conductive bands.

公开(公告)号：US20180108566A1

公开(公告)日：2018-04-19

申请号：US15837279

申请日：2017-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L49/02 ,  H01L23/498 ,  H01L23/48 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/311 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/90 ,  H01L28/92

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side and a back side, the substrate including a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate; etching the substrate on the back side of the substrate to remove at least a portion of the substrate on the back side; forming a first dielectric layer covering the back side of the substrate and extending away from the front side of the substrate; and forming a through silicon via (TSV) adjacent to the DT capacitor, the TSV extending through the first dielectric layer toward the front side of the substrate.

公开(公告)号：US09859382B2

公开(公告)日：2018-01-02

申请号：US14959825

申请日：2015-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/267 ,  H01L25/00 ,  H01L25/065 ,  H01L29/20 ,  H01L29/161 ,  H01L27/092 ,  H01L29/737

CPC classification number: H01L29/267 ,  H01L21/8258 ,  H01L23/3114 ,  H01L24/19 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/092 ,  H01L29/161 ,  H01L29/20 ,  H01L29/737 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2224/83

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.

公开(公告)号：US09825157B1

公开(公告)日：2017-11-21

申请号：US15196920

申请日：2016-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata A. Camillo-Castillo ,  Anthony K. Stamper

IPC: H01L29/73 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/737 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7378 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor with a stress component and methods of manufacture. The heterojunction bipolar transistor includes a collector region, an emitter region and a base region. Stress material is formed within a trench of a substrate and surrounding at least the collector region and the base region.