公开(公告)号：US06777713B2

公开(公告)日：2004-08-17

申请号：US10265634

申请日：2002-10-08

申请人： Hidekazu Miyairi ,  Aiko Shiga ,  Katsumi Nomura ,  Naoki Makita ,  Takuya Matsuo

发明人： Hidekazu Miyairi ,  Aiko Shiga ,  Katsumi Nomura ,  Naoki Makita ,  Takuya Matsuo

IPC分类号： H01L2900

CPC分类号： H01L27/12 ,  G02F1/1362 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L21/02686 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675

摘要： By adding a novel improvement to the technique disclosed in JP 8-78329 A, a manufacturing method in which film characteristics of a semiconductor film having a crystalline structure are improved is provided. In addition, a TFT having superior TFT characteristics, such as field effect mobility, which uses the semiconductor film as an active layer, and a method of manufacturing the TFT, are also provided. A metallic element which promotes the crystallization of silicon is added to a semiconductor film having an amorphous structure and an oxygen concentration within the film of less than 5×1018/cm3. The semiconductor film having an amorphous structure is then heat-treated, forming a semiconductor film having a crystalline structure. Subsequently, an oxide film on the surface is removed. Oxygen is introduced to the semiconductor film having a crystalline structure, and processing is performed such that the concentration of oxygen within the film is from 5×1018/cm3 to 1×1021/cm3. After removing an oxide film on the surface of the semiconductor film, the semiconductor film surface is leveled by irradiating laser light under an inert gas atmosphere or in a vacuum.

摘要翻译： 通过添加对JP 8-78329A中公开的技术的新颖改进，提供了具有改善晶体结构的半导体膜的膜特性的制造方法。 此外，还提供了具有优异TFT特性的TFT，例如使用半导体膜作为有源层的场效应迁移率，以及TFT的制造方法。 将促进硅结晶的金属元素加入到膜内的非晶结构和氧浓度小于5×10 18 / cm 3的半导体膜中。 然后对具有非晶结构的半导体膜进行热处理，形成具有晶体结构的半导体膜。 随后，除去表面上的氧化物膜。 将氧气引入具有晶体结构的半导体膜，并且进行处理，使得膜内的氧浓度为5×10 18 / cm 3至1×10 21 / cm 3。 在去除半导体膜表面上的氧化物膜之后，通过在惰性气体气氛或真空中照射激光来平整半导体膜表面。

公开(公告)号：US09312156B2

公开(公告)日：2016-04-12

申请号：US12726040

申请日：2010-03-17

申请人： Hidekazu Miyairi

发明人： Hidekazu Miyairi

IPC分类号： H01L29/786 ,  H01L21/67 ,  H01L27/12 ,  H01L29/04

CPC分类号： H01L21/67207 ,  H01L27/12 ,  H01L29/04 ,  H01L29/78618 ,  H01L29/78696

摘要： A thin film transistor includes a gate electrode; a gate insulating layer which is provided to cover the gate electrode; a semiconductor layer which is provided over the gate insulating layer to overlap with the gate electrode; an impurity semiconductor layer which is partly provided over the semiconductor layer and which forms a source region and a drain region; and a wiring layer which is provided over the impurity semiconductor layer, where a width of the source region and the drain region is narrower than a width of the semiconductor layer, and where the width of the semiconductor layer is increased at least in a portion between the source region and the drain region.

摘要翻译： 薄膜晶体管包括栅电极; 栅极绝缘层，被设置为覆盖栅电极; 半导体层，设置在所述栅极绝缘层上以与所述栅电极重叠; 部分地设置在半导体层上并形成源极区域和漏极区域的杂质半导体层; 以及布置层，其设置在所述杂质半导体层上，其中所述源极区域和所述漏极区域的宽度比所述半导体层的宽度窄，并且其中所述半导体层的宽度至少部分地在 源极区和漏极区。

公开(公告)号：US09230826B2

公开(公告)日：2016-01-05

申请号：US13213130

申请日：2011-08-19

申请人： Shinya Sasagawa ,  Hiroshi Fujiki ,  Shinobu Furukawa ,  Hidekazu Miyairi

发明人： Shinya Sasagawa ,  Hiroshi Fujiki ,  Shinobu Furukawa ,  Hidekazu Miyairi

IPC分类号： H01L21/20 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/32137 ,  H01L29/6675 ,  H01L29/66765 ,  H01L29/78663 ,  H01L29/78669 ,  H01L29/78672 ,  H01L29/78678 ,  H01L29/78687

摘要： A method for etching is provided in which the etching selectivity of an amorphous semiconductor film to a crystalline semiconductor film is high. Part of a stacked semiconductor film in which an amorphous semiconductor film is provided on a crystalline semiconductor film is etched using a mixed gas of a Br-based gas, a F-based gas, and an oxygen gas, so that part of the crystalline semiconductor film provided in the stacked semiconductor film is exposed. Reduction in the film thickness of the exposed portion can be suppressed by performing the etching in such a manner. Moreover, when etching for forming a back channel portion of a thin film transistor is performed with the method for etching, favorable electric characteristics of the thin film transistor can be obtained. An insulating layer is preferably provided over the thin film transistor.

摘要翻译： 提供了一种用于蚀刻的方法，其中非晶半导体膜对结晶半导体膜的蚀刻选择性高。 使用Br基气体，F系气体和氧气的混合气体蚀刻在结晶半导体膜上设置非晶半导体膜的层叠半导体膜的一部分，使部分结晶半导体 提供在堆叠的半导体膜中的膜被暴露。 可以通过以这种方式进行蚀刻来抑制曝光部分的膜厚度的降低。 此外，当利用蚀刻方法进行用于形成薄膜晶体管的背沟道部分的蚀刻时，可以获得薄膜晶体管的良好的电特性。 绝缘层优选设置在薄膜晶体管的上方。

公开(公告)号：US09178071B2

公开(公告)日：2015-11-03

申请号：US13225703

申请日：2011-09-06

申请人： Hidekazu Miyairi ,  Koji Dairiki ,  Shunpei Yamazaki ,  Ryo Arasawa

发明人： Hidekazu Miyairi ,  Koji Dairiki ,  Shunpei Yamazaki ,  Ryo Arasawa

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L29/78678 ,  H01L29/66765 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78669 ,  H01L29/78696

摘要： Provided is a method for manufacturing a semiconductor device with fewer masks and in a simple process. A gate electrode is formed. A gate insulating film, a semiconductor film, an impurity semiconductor film, and a conductive film are stacked in this order, covering the gate electrode. A source electrode and a drain electrode are formed by processing the conductive film. A source region, a drain region, and a semiconductor layer, an upper part of a portion of which does not overlap with the source region and the drain region is removed, are formed by processing the upper part of the semiconductor film, while the impurity semiconductor film is divided. A passivation film over the gate insulating film, the semiconductor layer, the source region, the drain region, the source electrode, and the drain electrode are formed. An etching mask is formed over the passivation film. At least the passivation film and the semiconductor layer are processed to have an island shape while an opening reaching the source electrode or the drain electrode is formed, with the use of the etching mask. The etching mask is removed. A pixel electrode is formed over the gate insulating film and the passivation film.

摘要翻译： 提供一种用于制造具有较少掩模的半导体器件的方法，并且在简单的过程中。 形成栅电极。 依次层叠栅绝缘膜，半导体膜，杂质半导体膜和导电膜，覆盖栅电极。 通过处理导电膜形成源电极和漏电极。 通过处理半导体膜的上部，形成源区域，漏极区域和半导体层，其部分的上部不与源极区域和漏极区域重叠，而杂质 半导体薄膜被划分。 形成栅极绝缘膜，半导体层，源极区域，漏极区域，源极电极和漏极电极之后的钝化膜。 在钝化膜上形成蚀刻掩模。 通过使用蚀刻掩模，至少钝化膜和半导体层被加工成具有岛状，同时形成到达源电极或漏电极的开口。 去除蚀刻掩模。 在栅极绝缘膜和钝化膜上形成像素电极。

公开(公告)号：US09111804B2

公开(公告)日：2015-08-18

申请号：US13346963

申请日：2012-01-10

申请人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Kengo Akimoto ,  Kojiro Shiraishi

发明人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Kengo Akimoto ,  Kojiro Shiraishi

IPC分类号： H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66969 ,  H01L21/46 ,  H01L27/1225 ,  H01L29/7869

摘要： It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

公开(公告)号：US09048147B2

公开(公告)日：2015-06-02

申请号：US13613811

申请日：2012-09-13

申请人： Shunpei Yamazaki ,  Takeshi Osada ,  Hidekazu Miyairi ,  Yasuhiro Jinbo

发明人： Shunpei Yamazaki ,  Takeshi Osada ,  Hidekazu Miyairi ,  Yasuhiro Jinbo

IPC分类号： G09G3/36 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

CPC分类号： G02F1/1368 ,  G02F1/133345 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/1365 ,  H01L27/1214 ,  H01L27/1229 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/04 ,  H01L29/78648 ,  Y10T428/24331

摘要： A display device of which frame can be narrowed and of which display characteristics are excellent is provided. In a display device including a switch portion or a buffer portion, a logic circuit portion, and a pixel portion, the pixel portion includes a first inverted staggered TFT and a pixel electrode which is connected to a wiring of the first inverted staggered TFT, the switch portion or the buffer portion includes a second inverted staggered TFT in which a first insulating layer, a semiconductor layer, and a second insulating layer are interposed between a first gate electrode and a second gate electrode, the logic circuit portion includes an inverter circuit including a third inverted staggered thin film transistor and a fourth inverted staggered thin film transistor, and the first to the fourth inverted staggered thin film transistors have the same polarity. The inverter circuit may be an EDMOS circuit.

摘要翻译： 提供了一种可以缩小框架并且显示特性优异的显示装置。 在包括开关部分或缓冲部分，逻辑电路部分和像素部分的显示装置中，像素部分包括连接到第一反交错TFT的布线的第一反交错TFT和像素电极， 开关部分或缓冲部分包括其中第一绝缘层，半导体层和第二绝缘层插入在第一栅电极和第二栅电极之间的第二反交错TFT，所述逻辑电路部分包括逆变器电路，包括 第三反交错薄膜晶体管和第四反交错薄膜晶体管，并且第一至第四反交错薄膜晶体管具有相同的极性。 逆变器电路可以是EDMOS电路。

公开(公告)号：US09029851B2

公开(公告)日：2015-05-12

申请号：US13302222

申请日：2011-11-22

申请人： Hidekazu Miyairi ,  Takeshi Osada ,  Shunpei Yamazaki

发明人： Hidekazu Miyairi ,  Takeshi Osada ,  Shunpei Yamazaki

IPC分类号： H01L27/088 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L29/7869 ,  H01L21/02565 ,  H01L21/47635 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648

摘要： As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

摘要翻译： 作为显示装置具有更高的清晰度，像素数，栅极线和信号线的数量增加。 当栅极线和信号线的数量增加时，由于难以通过接合等安装包括用于驱动栅极和信号线的驱动电路的IC芯片，所以制造成本更高。 用于驱动像素部分的像素部分和驱动电路设置在相同的基板上，驱动电路的至少一部分包括薄膜晶体管，该薄膜晶体管使用介于氧化物半导体上方和下方的栅电极之间的氧化物半导体。 因此，当像素部分和驱动器部分设置在相同的基板上时，可以降低制造成本。

公开(公告)号：US08907348B2

公开(公告)日：2014-12-09

申请号：US13478490

申请日：2012-05-23

申请人： Hidekazu Miyairi ,  Takeshi Osada ,  Shunpei Yamazaki

发明人： Hidekazu Miyairi ,  Takeshi Osada ,  Shunpei Yamazaki

IPC分类号： H01L27/14 ,  H01L27/12 ,  H01L29/786 ,  H01L27/32 ,  G02F1/1362

CPC分类号： H01L27/1225 ,  G02F1/1362 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/3262 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78606 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/7869

摘要： As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.

摘要翻译： 由于显示装置具有更高的清晰度，因此像素数量增加，因此栅极线和信号线的数量增加。 当栅极线和信号线的数量增加时，难以通过结合等安装包括用于驱动栅极线和信号线的驱动电路的IC芯片，由此增加制造成本。 用于驱动像素部分的像素部分和驱动电路设置在同一基板上，并且驱动电路的至少一部分包括薄膜晶体管，该薄膜晶体管包括夹在栅电极之间的氧化物半导体。 在氧化物半导体和设置在氧化物半导体上的栅电极之间设置沟道保护层。 像素部分和驱动电路设置在相同的基板上，这导致制造成本的降低。

公开(公告)号：US08778745B2

公开(公告)日：2014-07-15

申请号：US13159830

申请日：2011-06-14

申请人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi

发明人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L21/0262 ,  C23C16/0272 ,  C23C16/45523 ,  C23C16/515 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78648 ,  H01L29/78678 ,  H01L29/78696

摘要： A method for manufacturing a semiconductor device comprises the steps of forming a seed over the insulating film by introducing hydrogen and a deposition gas into a first treatment chamber under a first condition and forming a microcrystalline semiconductor film over the seed by introducing hydrogen and the deposition gas into a second treatment chamber under a second condition: a second flow rate of the deposition gas is periodically changed between a first value and a second value; and a second pressure in the second treatment chamber is higher than or equal to 1.0×102 Torr and lower than or equal to 1.0×103 Torr.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：通过在第一条件下将氢和沉积气体引入第一处理室中，在绝缘膜上形成晶种，并通过引入氢和沉积气体在晶种上形成微晶半导体膜 在第二条件下进入第二处理室：沉积气体的第二流量在第一值和第二值之间周期性地变化; 并且第二处理室中的第二压力高于或等于1.0×102乇并且小于或等于1.0×10 3乇。

公开(公告)号：US08729544B2

公开(公告)日：2014-05-20

申请号：US13013054

申请日：2011-01-25

申请人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Kengo Akimoto ,  Kojiro Shiraishi

发明人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Kengo Akimoto ,  Kojiro Shiraishi

IPC分类号： H01L29/22 ,  H01L29/786

CPC分类号： H01L29/66969 ,  H01L21/46 ,  H01L27/1225 ,  H01L29/7869

摘要： It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

摘要翻译： 本发明的目的是提供一种包括具有良好的电性能和高可靠性的薄膜晶体管的半导体器件，以及一种以高生产率制造半导体器件的方法。 在倒置交错（底栅极）薄膜晶体管中，使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且在半导体层和源之间设置使用金属氧化物层形成的缓冲层， 漏电极层。 有意地提供金属氧化物层作为半导体层与源极和漏极电极层之间的缓冲层，从而获得欧姆接触。