公开(公告)号：US20200321395A1

公开(公告)日：2020-10-08

申请号：US16635948

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Abhishek A. SHARMA ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Prashant MAJHI

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/12 ,  H01L45/00

Abstract: Embedded non-volatile memory structures having an independently sized selector element and memory element are described. In an example, a memory device includes a metal layer. A selector element is above the metal layer. A memory element is above the metal line. A spacer surrounds one of the selector element and the memory element having a smallest width, and wherein the one of the selector element and the memory element not surrounded by the spacer has a width substantially identical to the spacer and is in alignment with the spacer.

公开(公告)号：US20200227396A1

公开(公告)日：2020-07-16

申请号：US15754822

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sansaptak W. DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Ravi PILLARISETTY ,  Kimin JUN ,  Patrick MORROW ,  Valluri R. RAO ,  Paul B. FISCHER ,  Robert S. CHAU

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00

Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.

公开(公告)号：US20200212075A1

公开(公告)日：2020-07-02

申请号：US16633559

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Abhishek A. SHARMA ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768 ,  H01L21/027 ,  H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.

公开(公告)号：US20200168274A1

公开(公告)日：2020-05-28

申请号：US16636904

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Brian S. DOYLE ,  Elijah V. KARPOV ,  Prashant MAJHI

IPC: G11C13/00 ,  H01L27/24

Abstract: One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F2 or less density.

公开(公告)号：US20190355726A1

公开(公告)日：2019-11-21

申请号：US16480627

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Van H. LE ,  Gilbert DEWEY ,  Abhishek A. SHARMA

IPC: H01L27/108

Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

公开(公告)号：US20190229022A1

公开(公告)日：2019-07-25

申请号：US16372272

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack KAVALIEROS ,  Willy RACHMADY ,  Van LE ,  Benjamin CHU-KUNG ,  Matthew METZ ,  Robert CHAU

IPC: H01L21/84 ,  H01L21/8258 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/16 ,  H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US20190148491A1

公开(公告)日：2019-05-16

申请号：US16248708

申请日：2019-01-15

Applicant: Intel Corporation

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Harold Hal W. KENNEL ,  Willy RACHMADY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/161 ,  H01L29/15 ,  H01L29/165 ,  H01L29/10 ,  H01L21/283 ,  H01L21/02 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

公开(公告)号：US20180165065A1

公开(公告)日：2018-06-14

申请号：US15575334

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Charles C. KUO ,  Justin S. BROCKMAN ,  Juan G. ALZATE VINASCO ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Satyarth SURI ,  Robert S. CHAU ,  Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV

IPC: G06F7/58 ,  H01L43/08 ,  H01L43/02

CPC classification number: G06F7/588 ,  H01L43/02 ,  H01L43/08

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.

公开(公告)号：US20170162653A1

公开(公告)日：2017-06-08

申请号：US15433441

申请日：2017-02-15

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Harold W. KENNEL

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/165 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/1083 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78696

Abstract: Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate electrode stack disposed above a substrate. A germanium active layer is disposed above the substrate, underneath the gate electrode stack. A diffusion barrier layer is disposed above the substrate, below the germanium active layer. A junction leakage suppression layer is disposed above the substrate, below the diffusion barrier layer. Source and drain regions are disposed above the junction leakage suppression layer, on either side of the gate electrode stack.

公开(公告)号：US20170047401A1

公开(公告)日：2017-02-16

申请号：US15334112

申请日：2016-10-25

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Van H. LE ,  Ravi PILLARISETTY ,  Jessica S. KACHIAN ,  Marc C. FRENCH ,  Aaron A. BUDREVICH

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/167 ,  H01L29/66 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

Abstract translation: 在那里制造的半导体器件堆叠和器件具有富锗器件层。 富锗器件层设置在衬底上方，其间布置有p型掺杂Ge蚀刻抑制层（例如，p型SiGe），以在去除牺牲半导体层期间抑制富锗器件层的蚀刻 Si比设备层更丰富。 随着在半导体膜堆叠中引入掩埋的p型掺杂半导体层，可以显着降低Ge在湿蚀刻剂（例如氢氧化物水溶液）中的溶解速率，从而提高蚀刻剂对Ge富集器件层的选择性。