公开(公告)号：US09831324B1

公开(公告)日：2017-11-28

申请号：US15235357

申请日：2016-08-12

Applicant: International Business Machines Corporation

Inventor： Robin Hsin-Kuo Chao ,  Michael A. Guillorn ,  Chi-Chun Liu ,  Shogo Mochizuki ,  Chun W. Yeung

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/66818 ,  H01L21/26513 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/7853

Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region.

公开(公告)号：US09810980B1

公开(公告)日：2017-11-07

申请号：US15426523

申请日：2017-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  TOKYO ELECTRON LIMITED

Inventor： Hongyun Cottle ,  Cheng Chi ,  Chi-Chun Liu ,  Kristin Schmidt

IPC: C03C15/00 ,  G03F7/00 ,  C30B1/04 ,  C30B29/58 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105

CPC classification number: G03F7/0002 ,  B81C1/00031 ,  B81C1/00396 ,  B81C1/00531 ,  B81C2201/0149 ,  C09K13/00 ,  C30B1/04 ,  C30B7/005 ,  C30B29/58 ,  C30B33/08 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/302 ,  H01L21/31058 ,  H01L21/31133

Abstract: Graphoepitaxy directed self-assembly methods generally include grafting a conformal layer of a polymer brush onto a topographic substrate. A planarization material, which functions as a sacrificial material is coated onto the topographic substrate. The planarization material is etched back to a top surface of the topographic substrate, wherein the etch back removes the polymer brush from the top surfaces of the topographic substrate. The remaining portion of the polymer brush is protected by the remaining planarization material below the top surface of the topographic substrate, which can be removed with a solvent to provide the topographic substrate with a conformal polymer brush below the top surface of the topographic substrate. The substrate is then coated with a block copolymer and annealed to direct self-assembly of the block copolymer. The methods mitigate island and/or hole defect formation.

公开(公告)号：US20170294341A1

公开(公告)日：2017-10-12

申请号：US15092693

申请日：2016-04-07

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Teddie P. Magbitang ,  Daniel P. Sanders ,  Kristin Schmidt ,  Ankit Vora

IPC: H01L21/768 ,  C23F1/00 ,  C08G81/02

CPC classification number: H01L21/0274 ,  B82Y10/00 ,  B82Y40/00 ,  C08G81/027 ,  G03F7/0002 ,  G03F7/002 ,  G03F7/165 ,  G03F7/20 ,  G03F7/2022 ,  G03F7/2059 ,  G03F7/32 ,  G03F7/40 ,  H01L21/02112 ,  H01L21/0271 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/76816

Abstract: High-chi diblock copolymers are disclosed whose self-assembly properties are suitable for forming hole and bar openings for conductive interconnects in a multi-layered structure. The hole and bar openings have reduced critical dimension, improved uniformity, and improved placement error compared to the industry standard poly(styrene)-b-poly(methyl methacrylate) block copolymer (PS-b-PMMA). The BCPs comprise a poly(styrene) block, which can optionally include repeat units derived from trimethylsilyl styrene, and a second block that can be a polycarbonate block or a polyester block. Block copolymers comprising a fluorinated linking group L′ comprising 1-25 fluorines between the blocks can provide further improvement in uniformity of the openings.

公开(公告)号：US09536750B1

公开(公告)日：2017-01-03

申请号：US14870932

申请日：2015-09-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0692

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

Abstract translation: 制造半导体器件的方法包括在衬底上设置第一硬掩模（HM），非晶硅和第二HM; 在第二HM上设置氧化物和中性层; 去除所述氧化物和中性层的一部分以暴露所述第二HM的一部分; 通过选择性地回填聚合物形成引导图案; 在引导图案上形成自组装嵌段共聚物（BCP）; 去除BCP的一部分以形成蚀刻模板; 将图案从所述模板转移到衬底中并且形成具有不同材料和高度的两种类型的HM堆叠的均匀硅片阵列; 填充氧化物，然后平坦化; 用第三HM材料选择性地去除和更换较高的HM堆叠; 平坦化表面并暴露两个HM堆叠; 并选择性地去除下面的较短的HM堆叠和硅片。

公开(公告)号：US09490168B1

公开(公告)日：2016-11-08

申请号：US14710894

申请日：2015-05-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US12046680B2

公开(公告)日：2024-07-23

申请号：US17485765

申请日：2021-09-27

Applicant: International Business Machines Corporation

Inventor： Yi Song ,  Chi-Chun Liu ,  Robin Hsin Kuo Chao ,  Muthumanickam Sankarapandian

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality of gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.

公开(公告)号：US11682558B2

公开(公告)日：2023-06-20

申请号：US17481981

申请日：2021-09-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Ashim Dutta ,  Nelson Felix ,  Ekmini Anuja De Silva

IPC: H01L21/311 ,  H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/31111

Abstract: A semiconductor structure includes a set of mandrel lines and a set of non-mandrel lines disposed on a hardmask in an alternating pattern. Spacers are disposed between adjacent mandrel lines and non-mandrel lines. The spacers include a composition which exhibits an etch rate greater than an etch rate of the mandrel lines and the non-mandrel lines.

公开(公告)号：US11329001B2

公开(公告)日：2022-05-10

申请号：US16413208

申请日：2019-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Chi-Chun Liu

IPC: H01L23/544 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/311

Abstract: A security region is provided. The security region includes a plurality of parallel conductive lines on a substrate, wherein each of the parallel conductive lines has a width and includes a bend, and wherein at least a portion of the plurality of parallel conductive lines is discontinuous, and an electrically insulating material between each adjacent pair of parallel conductive lines.

公开(公告)号：US11195995B2

公开(公告)日：2021-12-07

申请号：US16735020

申请日：2020-01-06

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Yann Mignot ,  Ekmini Anuja De Silva ,  Nelson Felix ,  John Christopher Arnold

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.

公开(公告)号：US11139242B2

公开(公告)日：2021-10-05

申请号：US16397250

申请日：2019-04-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chih-Chao Yang ,  Chi-Chun Liu ,  Kangguo Cheng

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/311

Abstract: Integrated chips and methods for forming vias in the same include forming a multi-layer isolation structure on an underlying layer. The multi-layer isolation structure includes a first isolation layer around a second isolation layer. Conductive material is formed around the multi-layer isolation structure. The first isolation layer is etched back to expose at least a portion of a sidewall of the conductive material. A conductive via is formed to contact a top surface and the exposed portion of the sidewall of the conductive material.