公开(公告)号：US20250008685A1

公开(公告)日：2025-01-02

申请号：US18216049

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Nirmala Bailur ,  Min Suet Lim ,  Tongyan Zhai ,  Chee Chun Yee ,  Ruander Cardenas ,  Lance Lin ,  Eng Huat Goh ,  Javed Shaikh ,  Jun Liao ,  Kavitha Nagarajan ,  Tin Poay Chuah ,  Martin M. Chang ,  Shantanu D. Kulkarni ,  Telesphor Kamgaing

IPC: H05K7/20 ,  F04D19/00 ,  F04D29/52 ,  G06F1/20

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for cooling electronic devices. An example apparatus includes a fan module for an electronic device. The fan module includes a first cover; a second cover; an input/output (IO) board adjacent the second cover, the second cover and IO board beneath the first cover; and a fan between the first cover and the second cover, the fan to operate above the second cover and a portion of the IO board.

公开(公告)号：US12156331B2

公开(公告)日：2024-11-26

申请号：US17212016

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Khai Ern See ,  Jia Lin Liew ,  Tin Poay Chuah ,  Chee How Lim ,  Yi How Ooi

IPC: H05K1/02 ,  H01L21/3105 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42

Abstract: Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.

公开(公告)号：US12033953B2

公开(公告)日：2024-07-09

申请号：US16830853

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Tin Poay Chuah ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3025

Abstract: A substrate may be included in an electronic device. The substrate may include a first layer that may include a dielectric material. The first layer may define a substrate surface. The substrate may include a second layer optionally including the dielectric material. The second layer may be coupled to the first layer. A wiring trace may be located in the substrate. A recess may extend through the substrate surface, the first layer, and may extend through the second layer. A substrate interconnect may be located within the recess. The substrate interconnect may be at least partially located below the substrate surface. The substrate interconnect may be in electrical communication with the wiring trace.

公开(公告)号：US20240006399A1

公开(公告)日：2024-01-04

申请号：US17853329

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Chan Kim Lee ,  Eng Huat Goh ,  Jenny Shio Yin Ong ,  Tin Poay Chuah

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/552

CPC classification number: H01L25/18 ,  H01L25/0652 ,  H01L23/3185 ,  H01L23/367 ,  H01L25/50 ,  H01L21/56 ,  H01L21/486 ,  H01L23/552 ,  H01L23/5386

Abstract: An electronic device includes a package substrate; a memory integrated circuit (IC) mounted on the package substrate; a mold layer including one or more chiplets and a base IC die within the mold layer, the one or more chiplets arranged on the base IC die; a top chiplet mounted on a surface of the mold layer, wherein a combined height of the mold layer and the top chiplet substantially matches a height of the memory IC; and a heat spreader having a uniform surface contacting the memory IC and the top chiplet.

公开(公告)号：US11445608B2

公开(公告)日：2022-09-13

申请号：US16903845

申请日：2020-06-17

Applicant: Intel Corporation

Inventor： Chee How Lim ,  Eng Huat Goh ,  Jon Sern Lim ,  Khai Ern See ,  Min Suet Lim ,  Tin Poay Chuah ,  Yew San Lim

IPC: H05K1/14 ,  H01R12/61 ,  H05K1/11

Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.

公开(公告)号：US11355427B2

公开(公告)日：2022-06-07

申请号：US16095916

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Sujit Sharan ,  Tin Poay Chuah ,  Ananth Prabhakumar

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L21/48 ,  H01L21/768 ,  H05K1/18 ,  H01L25/065

Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.

公开(公告)号：US11304299B2

公开(公告)日：2022-04-12

申请号：US17008222

申请日：2020-08-31

Applicant: Intel Corporation

Inventor： Chee Ling Wong ,  Wil Choon Song ,  Khang Choong Yong ,  Eng Huat Goh ,  Mohd Muhaiyiddin Bin Abdullah ,  Tin Poay Chuah

IPC: H05K1/11 ,  H05K1/14 ,  H05K1/02

Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

公开(公告)号：US20210410341A1

公开(公告)日：2021-12-30

申请号：US17471396

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Boon Ping Koh ,  Twan Sing Loo ,  Yew San Lim ,  Tin Poay Chuah

IPC: H05K9/00 ,  H05K1/02

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a support structure that includes a radiation shield groove that extends past a surface of the support structure and into the support structure, a radiation source on the substrate, and a radiation shield around the radiation source, where the radiation shield includes a wall secured to the support structure and a groove channel coupling wall that extends past a surface of the support structure and into the radiation shield groove.

公开(公告)号：US20210100101A1

公开(公告)日：2021-04-01

申请号：US16903845

申请日：2020-06-17

Applicant: Intel Corporation

Inventor： Chee How Lim ,  Eng Huat Goh ,  Jon Sern Lim ,  Khai Ern See ,  Min Suet Lim ,  Tin Poay Chuah ,  Yew San Lim

IPC: H05K1/14 ,  H05K1/11 ,  H01R12/61

Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.

公开(公告)号：US20210028094A1

公开(公告)日：2021-01-28

申请号：US17069421

申请日：2020-10-13

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Min Suet Lim ,  Tin Poay Chuah

IPC: H01L23/498 ,  H05K1/18 ,  H05K1/14 ,  H05K3/36 ,  H01L23/538 ,  H05K3/46

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.