公开(公告)号：US08889511B2

公开(公告)日：2014-11-18

申请号：US13219229

申请日：2011-08-26

申请人： Joseph A. Yedinak ,  Nathan L. Kraft

发明人： Joseph A. Yedinak ,  Nathan L. Kraft

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/40 ,  H01L29/739 ,  H01L21/683 ,  H01L21/311 ,  H02M3/335 ,  H01L29/49 ,  H01L23/498 ,  H01L29/423 ,  H01L29/165 ,  H01L21/265 ,  H02M3/00 ,  H01L29/417 ,  H02M7/48 ,  H01L23/495 ,  H01L29/10

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： In one general aspect, a method can include forming a shield dielectric layer in a trench in a semiconductor substrate, forming a shield electrode on at least a portion of the shield dielectric layer, and etching the shield dielectric layer so that a portion of the shield dielectric layer is recessed in the trench. The method can include forming a gate dielectric layer on the recessed portion of the shield dielectric layer in the trench, forming a first conductive gate electrode on a first side of the shield electrode and insulated from a first sidewall of the trench by the gate dielectric layer, and forming a second conductive gate electrode on a second side of the shield electrode and insulated from a second sidewall of the trench by the gate dielectric layer.

摘要翻译： 在一个一般方面，一种方法可以包括在半导体衬底中的沟槽中形成屏蔽电介质层，在屏蔽电介质层的至少一部分上形成屏蔽电极，以及蚀刻屏蔽电介质层，使屏蔽层的一部分 电介质层凹陷在沟槽中。 该方法可以包括在沟槽中的屏蔽电介质层的凹陷部分上形成栅极电介质层，在屏蔽电极的第一侧上形成第一导电栅电极，并通过栅介质层与沟槽的第一侧壁绝缘 并且在屏蔽电极的第二侧上形成第二导电栅电极，并通过栅介质层与沟槽的第二侧壁绝缘。

公开(公告)号：US08803207B2

公开(公告)日：2014-08-12

申请号：US13081400

申请日：2011-04-06

申请人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley ,  Gary M. Dolny ,  Joseph A. Yedinak ,  Christopher Boguslaw Kocon ,  Ashok Challa

发明人： Thomas E. Grebs ,  Nathan Lawrence Kraft ,  Rodney Ridley ,  Gary M. Dolny ,  Joseph A. Yedinak ,  Christopher Boguslaw Kocon ,  Ashok Challa

IPC分类号： H01L29/76 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.

摘要翻译： 在一个一般方面，一种装置可以包括设置在半导体区域中的沟槽，衬在沟槽的侧壁的下部的屏蔽电介质层和沟槽的底表面，以及衬在该侧壁的上部的栅极电介质 的沟槽。 该设备还可以包括设置在沟槽的下部并由屏蔽电介质层与半导体区域绝缘​​的屏蔽电极，以及设置在屏蔽电极上的沟槽中的电极间电介质（IED），其中屏蔽电极具有 一个弯曲的顶面。

公开(公告)号：US08441069B2

公开(公告)日：2013-05-14

申请号：US13279085

申请日：2011-10-21

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Boguslaw Kocon ,  Steven P. Sapp ,  Dean E. Probst ,  Nathan L. Kraft ,  Thomas E. Grebs ,  Rodney S. Ridley ,  Gary M. Dolny ,  Bruce D. Marchant ,  Joseph A. Yedinak

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Boguslaw Kocon ,  Steven P. Sapp ,  Dean E. Probst ,  Nathan L. Kraft ,  Thomas E. Grebs ,  Rodney S. Ridley ,  Gary M. Dolny ,  Bruce D. Marchant ,  Joseph A. Yedinak

IPC分类号： H01L29/772

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A field effect transistor includes a gate trench extending into a semiconductor region. The gate trench has a recessed gate electrode disposed therein. A source region in the semiconductor region flanks each side of the gate trench. A conductive material fills an upper portion of the gate trench so as to make electrical contact with the source regions along upper sidewalls of the gate trench. The conductive material is insulated from the recessed gate electrode.

摘要翻译： 场效应晶体管包括延伸到半导体区域中的栅极沟槽。 栅极沟槽具有设置在其中的凹陷栅电极。 半导体区域中的源极区域位于栅极沟槽的每一侧。 导电材料填充栅极沟槽的上部，以便沿着栅极沟槽的上侧壁与源极区域电接触。 导电材料与凹陷栅电极绝缘。

公开(公告)号：US08357976B2

公开(公告)日：2013-01-22

申请号：US12974599

申请日：2010-12-21

申请人： Joseph A. Yedinak ,  Richard L. Woodin ,  Christopher L. Rexer ,  Praveen Muralheedaran Shenoy ,  Kwanghoon Oh ,  Chongman Yun

发明人： Joseph A. Yedinak ,  Richard L. Woodin ,  Christopher L. Rexer ,  Praveen Muralheedaran Shenoy ,  Kwanghoon Oh ,  Chongman Yun

IPC分类号： H01L27/02

CPC分类号： H01L29/872 ,  H01L27/0248 ,  H01L29/1608 ,  H01L29/8618 ,  H01L29/87

摘要： An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer.

摘要翻译： 单个半导体衬底上的电子器件包括：与宽带隙高压二极管并联放置的开放式基极垂直PNP晶体管，其中PNP晶体管具有P掺杂集电极区，N掺杂基极层，N掺杂缓冲层 和P掺杂发射极层。

公开(公告)号：US20120276701A1

公开(公告)日：2012-11-01

申请号：US13095678

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/872

摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

公开(公告)号：US20120220091A1

公开(公告)日：2012-08-30

申请号：US13418128

申请日：2012-03-12

申请人： Ashok Challa ,  Alan Elbanhawy ,  Thomas E. Grebs ,  Nathan L. Kraft ,  Dean E. Probst ,  Rodney S. Ridley ,  Steven P. Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter H. Wilson ,  Joseph A. Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak S. Sani ,  Richard Stokes ,  Gary M. Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James J. Murphy ,  Gordon K. Madson ,  Bruce D. Marchant ,  Christopher L. Rexer ,  Christopher B. Kocon ,  Debra S. Woolsey

发明人： Ashok Challa ,  Alan Elbanhawy ,  Thomas E. Grebs ,  Nathan L. Kraft ,  Dean E. Probst ,  Rodney S. Ridley ,  Steven P. Sapp ,  Qi Wang ,  Chongman Yun ,  J.G. Lee ,  Peter H. Wilson ,  Joseph A. Yedinak ,  J.Y. Jung ,  H.C. Jang ,  Babak S. Sani ,  Richard Stokes ,  Gary M. Dolny ,  John Mytych ,  Becky Losee ,  Adam Selsley ,  Robert Herrick ,  James J. Murphy ,  Gordon K. Madson ,  Bruce D. Marchant ,  Christopher L. Rexer ,  Christopher B. Kocon ,  Debra S. Woolsey

IPC分类号： H01L21/336 ,  H01L21/311

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.

摘要翻译： 在半导体衬底中形成的沟槽的底部形成厚氧化物的方法包括通过填充沟槽并覆盖衬底顶表面的亚大气压化学气相沉积工艺形成共形氧化膜。 该方法还包括将氧化膜从衬底的顶表面和沟槽内部蚀刻，以留下在沟槽底部具有目标厚度的基本平坦的氧化物层。

公开(公告)号：US20120104490A1

公开(公告)日：2012-05-03

申请号：US13279085

申请日：2011-10-21

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Boguslaw Kocon ,  Steven P. Sapp ,  Dean E. Probst ,  Nathan L. Kraft ,  Thomas E. Grebs ,  Rodney S. Ridley ,  Gary M. Dolny ,  Bruce D. Marchant ,  Joseph A. Yedinak

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Boguslaw Kocon ,  Steven P. Sapp ,  Dean E. Probst ,  Nathan L. Kraft ,  Thomas E. Grebs ,  Rodney S. Ridley ,  Gary M. Dolny ,  Bruce D. Marchant ,  Joseph A. Yedinak

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

摘要翻译： 场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的体区。 栅极沟槽延伸穿过身体区域并终止在半导体区域内。 至少一个导电屏蔽电极设置在栅极沟槽中。 栅极电极设置在栅极沟槽中，但与至少一个导电屏蔽电极绝缘。 屏蔽介电层绝缘至少一个导电屏蔽电极与半导体区域。 栅极电介质层使栅电极与体区绝缘。 屏蔽电介质层形成为使其伸出并直接延伸到身体区域下方。

公开(公告)号：US20120037982A1

公开(公告)日：2012-02-16

申请号：US13283496

申请日：2011-10-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/407 ,  H01L29/36 ,  H01L29/8725

摘要： Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

摘要翻译： 公开了制造半导体器件的半导体器件和方法。 示例性实施例包括第一导电类型的半导体层，其具有在半导体层的一部分内的第一导电类型的第一表面，第二表面和等级净掺杂浓度。 分级部分位于与半导体层的顶表面相邻的位置，并且其中的渐变网络掺杂浓度随距离半导体层的顶表面的距离而减小。 示例性器件还包括设置在半导体层的第一表面并且与渐变部分相邻的电极。

公开(公告)号：US20110312166A1

公开(公告)日：2011-12-22

申请号：US13219281

申请日：2011-08-26

申请人： Joseph A. Yedinak ,  Nathan L. Kraft ,  Christopher B. Kocon ,  Richard Stokes

发明人： Joseph A. Yedinak ,  Nathan L. Kraft ,  Christopher B. Kocon ,  Richard Stokes

IPC分类号： H01L21/20

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Methods of manufacturing power semiconductor devices include forming an epitaxial and dielectric layer, patterning and etching the dielectric layer, forming a first oxide layer, forming a first conductive layer on top of the first oxide layer, etching the first conductive layer away inside an active trench, forming a second oxide layer and second conductive layer. The second conductive layer does not extend completely over the first conductive layer in a first region outside of the active trench. The methods further include forming a third oxide layer over the second conductive layer, etching a first opening through the third oxide layer exposing the second conductive layer outside the active trench, etching a second opening through the second oxide layer outside the active trench in the first region exposing the first conductive layer but not the second conductive layer, and filling the first and second openings with conductive material.

摘要翻译： 制造功率半导体器件的方法包括形成外延和电介质层，图案化和蚀刻介电层，形成第一氧化物层，在第一氧化物层的顶部形成第一导电层，在有源沟槽内部蚀刻第一导电层 ，形成第二氧化物层和第二导电层。 第二导电层在有源沟槽外部的第一区域中不完全延伸到第一导电层上。 所述方法还包括在所述第二导电层上形成第三氧化物层，蚀刻通过所述第三氧化物层的第一开口，将所述第二导电层暴露于所述有源沟槽外部，在所述第一导电层中的所述有源沟槽外蚀刻穿过所述第二氧化物层的第二开口 区域暴露第一导电层而不暴露第二导电层，以及用导电材料填充第一和第二开口。

公开(公告)号：US20110312138A1

公开(公告)日：2011-12-22

申请号：US13219229

申请日：2011-08-26

申请人： Joseph A. Yedinak ,  Nathan L. Kraft

发明人： Joseph A. Yedinak ,  Nathan L. Kraft

IPC分类号： H01L21/336

CPC分类号： H01L29/407 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2924/00014

摘要： Methods of manufacturing power semiconductor devices include forming trenches in a substrate, depositing a shield oxide layer that conforms to the trenches, depositing a gate polysilicon layer into the trenches, etching the gate polysilicon layer so that the gate polysilicon layer is recessed in the trench, etching the shield oxide layer so that the shield oxide layer is recessed in the trench and lower than the gate polysilicon layer, depositing a layer of gate oxide across the top of the substrate, sidewalls of the trenches and troughs inside the trenches leaving a recess, depositing shield polysilicon in the recess, etching the shield polysilicon layer so that the shield polysilicon layer is recessed in the trench and higher than the gate polysilicon layer, forming a well region, and forming a source region. The well region can be formed with a −p-well implant. The source region can be performed with an n+ source implant.

摘要翻译： 制造功率半导体器件的方法包括在衬底中形成沟槽，沉积符合沟槽的屏蔽氧化物层，在栅极中沉积栅极多晶硅层，蚀刻栅极多晶硅层，使得栅极多晶硅层在沟槽中凹陷， 蚀刻屏蔽氧化物层，使得屏蔽氧化物层凹陷在沟槽中并且低于栅极多晶硅层，在栅极的顶部沉积栅极氧化物层，沟槽的侧壁和槽内的沟槽离开凹槽， 将屏蔽多晶硅沉积在凹槽中，蚀刻屏蔽多晶硅层，使得屏蔽多晶硅层凹陷在沟槽中并且高于栅极多晶硅层，形成阱区，并形成源极区。 阱区可以用-p-阱植入物形成。 源区域可以用n +源植入物进行。