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69 条记录 (耗时 0.024 秒)

    Clocked cycle latch circuit
    54.
    发明授权
    Clocked cycle latch circuit 失效
    时钟周期锁存电路

    公开(公告)号：US06970018B2

    公开(公告)日：2005-11-29

    申请号：US10873243

    申请日：2004-06-23

    申请人： Dejan Markovic ,  James W. Tschanz ,  Vivek K. De

    发明人： Dejan Markovic ,  James W. Tschanz ,  Vivek K. De

    IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K3/356 ,  H03K19/094

    CPC分类号： H03K3/356113 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356156

    摘要： A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

    摘要翻译： 循环锁存器包括控制电路，其通过在交叉耦合的逆变器保持器结构中有条件地排放反馈节点来增加存储节点的上拉率。 周期锁存器包括用于将输入值传送到存储节点的NMOS晶体管开关和串联连接的两个NMOS晶体管，用于执行控制电路的功能。 通过将存储节点连接到预放电反馈节点，然后用低摆频时钟驱动锁存器，实现延迟时间，能量消耗和鲁棒性方面的改进的性能。

    Time-borrowing N-only clocked cycle latch
    55.
    发明授权
    Time-borrowing N-only clocked cycle latch 有权

    公开(公告)号：US06806739B2

    公开(公告)日：2004-10-19

    申请号：US10330544

    申请日：2002-12-30

    申请人： Dejan Markovic ,  James W. Tschanz ,  Vivek K. De

    发明人： Dejan Markovic ,  James W. Tschanz ,  Vivek K. De

    IPC分类号： H03K19094

    CPC分类号： H03K3/356113 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356156

    摘要： A cycle latch includes a control circuit which increases the pull-up rate of a storage node by conditionally discharging the feedback node in a cross-coupled inverter keeper structure. The cycle latch includes an NMOS transistor switch for transferring an input value to the storage node, and two more NMOS transistors connected in series for performing the function of the control circuit. By connecting the storage node to a pre-discharged feedback node and then driving the latch with a low-swing clock, improved performance in terms of delay times, energy consumption, and robustness is achieved.

    MULTI-SUPPLY SEQUENTIAL LOGIC UNIT
    56.
    发明申请
    MULTI-SUPPLY SEQUENTIAL LOGIC UNIT 有权
    多供应序列逻辑单元

    公开(公告)号：US20140218069A1

    公开(公告)日：2014-08-07

    申请号：US13992894

    申请日：2011-12-14

    申请人： Arijit Raychowdhury ,  Jaydeep P. Kulkarni ,  James W. Tschanz

    发明人： Arijit Raychowdhury ,  Jaydeep P. Kulkarni ,  James W. Tschanz

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017509 ,  G06F1/10 ,  G06F1/3296 ,  Y02D10/172

    摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.

    摘要翻译： 这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置，方法和系统。 所述装置包括顺序单元，包括：数据路径，用于接收输入信号，包括在第一电源电平上操作的逻辑门，所述数据路径以产生输出信号; 以及时钟路径，包括用于在第二电源电平上操作的逻辑门，所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号，其中所述第二电源电平高于所述第一电力 供应水平。 该装置改善（即减少）顺序单元的建立时间，并允许处理器以最小工作电压（Vmin）运行，而不降低顺序单元的性能。

    Component reliability budgeting system
    60.
    发明授权
    Component reliability budgeting system 有权
    组件可靠性预算系统

    公开(公告)号：US08312306B2

    公开(公告)日：2012-11-13

    申请号：US12704789

    申请日：2010-02-12

    申请人： Siva G. Narendra ,  James W. Tschanz ,  Vivek K. De ,  Stephen H. Tang

    发明人： Siva G. Narendra ,  James W. Tschanz ,  Vivek K. De ,  Stephen H. Tang

    IPC分类号： G06F1/26 ,  G06F15/18 ,  G06F11/00 ,  G05B9/02 ,  G01R21/00 ,  G01R19/00 ,  G01K1/08

    CPC分类号： G06F1/206 ,  Y02D10/16

    摘要： A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.

    摘要翻译： 系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及 温度信息。 一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。