公开(公告)号：US08024012B2

公开(公告)日：2011-09-20

申请号：US12137185

申请日：2008-06-11

申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens

发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Carl Radens

IPC分类号： H04B1/38 ,  H04B1/16

CPC分类号： H02J50/20 ,  H02J7/025 ,  H02J17/00

摘要： A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.

摘要翻译： 一种用于无线网络设备智能电源管理的系统和方法。 该系统通过无线电力充电方法提供可靠的无线通信，以及在无线设备中维持电池的电力容量的方法。 电池通过嵌入在无线设备内部的射频收集单元进行充电。 智能无线电力充电系统还包括耦合到AC电力线的至少两个电池和至少两个RF适配器装置。 第一个适配器设置为数据通信，而第二个适配器用于传输电源。 此外，当在活动模式期间使用第一电池时，对第二电池进行无线充电。

公开(公告)号：US20050127514A1

公开(公告)日：2005-06-16

申请号：US10731377

申请日：2003-12-08

申请人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Timothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

发明人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Timothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

摘要翻译： 在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。 在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

公开(公告)号：US20050067702A1

公开(公告)日：2005-03-31

申请号：US10674646

申请日：2003-09-30

申请人： William America ,  Timothy Dalton ,  Kaushik Kumar ,  Heidi Wickland

发明人： William America ,  Timothy Dalton ,  Kaushik Kumar ,  Heidi Wickland

IPC分类号： H01L21/033 ,  H01L21/312 ,  H01L21/768 ,  H01L21/4763 ,  H01L23/02 ,  H01L29/40

CPC分类号： H01L21/02126 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/0332 ,  H01L21/3122 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829

摘要： Interconnect structure having enhanced adhesion between the various interfaces encompassing an organo-silicate glass (OSG) film, for use in semiconductor devices is provided herein. The novel interconnect structure includes a non-damaged plasma-treated low-k OSG surface to enhance the adhesion of the hardmask material to the OSG surface, and an unique deposition scheme for the hardmasks in order to make the entire structure pliant towards implementing mild processing condition during the reactive ion etch patterning of the dielectric structure in a damascene and dual-damascene scheme. The methods for making a semiconductor device having an enhanced adhesion and micromasks free profiles are also provided.

摘要翻译： 本文提供了在包括用于半导体器件的有机硅酸盐玻璃（OSG）膜的各种界面之间具有增强的粘附性的互连结构。 新颖的互连结构包括未损坏的等离子体处理的低k OSG表面，以增强硬掩模材料对OSG表面的粘附性，以及用于硬掩模的独特沉积方案，以使整个结构趋于实现温和加工 在大马士革和双镶嵌方案中的电介质结构的反应离子蚀刻图案化期间的条件。 还提供了制造具有增强的粘合性和微掩模免费型材的半导体器件的方法。

公开(公告)号：US20050167838A1

公开(公告)日：2005-08-04

申请号：US10707996

申请日：2004-01-30

申请人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

发明人： Daniel Edelstein ,  Matthew Colburn ,  Edward Cooney ,  Timothy Dalton ,  John Fitzsimmons ,  Jeffrey Gambino ,  Elbert Huang ,  Michael Lane ,  Vincent McGahay ,  Lee Nicholson ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas Shaw ,  Andrew Simon ,  Anthony Stamper

IPC分类号： H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线车道和通道上或附近形成间隙

公开(公告)号：US09059000B2

公开(公告)日：2015-06-16

申请号：US12106586

申请日：2008-04-21

申请人： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

发明人： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  G03F7/11

CPC分类号： H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

公开(公告)号：US20070241398A1

公开(公告)日：2007-10-18

申请号：US11277306

申请日：2006-03-23

申请人： Timothy Dalton ,  Marc Faucher ,  Paul Kartschoke ,  Peter Sandon

发明人： Timothy Dalton ,  Marc Faucher ,  Paul Kartschoke ,  Peter Sandon

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L25/0657 ,  G01R31/318513 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.

摘要翻译： 半导体结构及其操作方法。 半导体结构包括第一半导体芯片和第二半导体芯片。 第一半导体芯片位于第二半导体芯片的顶部并结合到第二半导体芯片上。 第一和第二半导体芯片包括第一和第二电节点。 第二半导体芯片还包括第一比较电路。 半导体结构还包括通过将第一半导体芯片的第一电节点电连接到第二半导体芯片的第一比较电路的第一耦合。 第一比较电路能够（i）直接从第二电节点接收输入信号，（ii）通过第一耦合通路间接接收来自第一电节点的输入信号，以及（iii）将第一不匹配信号置于 对来自第一和第二电节点的输入信号的响应是不同的。

公开(公告)号：US20060258147A1

公开(公告)日：2006-11-16

申请号：US11405287

申请日：2006-04-17

申请人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Anna Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

发明人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Anna Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

公开(公告)号：US20060094230A1

公开(公告)日：2006-05-04

申请号：US10904323

申请日：2004-11-04

申请人： Nicholas Fuller ,  Timothy Dalton ,  Raymond Joy ,  Yi-hsiung Lin ,  Chun Low

发明人： Nicholas Fuller ,  Timothy Dalton ,  Raymond Joy ,  Yi-hsiung Lin ,  Chun Low

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/0332 ,  H01L21/31138 ,  H01L21/31144

摘要： Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.

摘要翻译： 公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。 该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层 层。 有机材料和无机材料之间的材料类型是交替的。 第三层被图案化为金属线和/或经由CD。 然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。 提供准确的CD形成和足够的抗蚀剂预算。

公开(公告)号：US20050266681A1

公开(公告)日：2005-12-01

申请号：US11182445

申请日：2005-07-15

申请人： Timothy Dalton ,  Stephen Gates

发明人： Timothy Dalton ,  Stephen Gates

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/02063 ,  H01L21/76814

摘要： A method of fabricating BEOL interconnect structures on a semiconductor device having a plurality of via contacts with low via contact resistance is provided. The method includes the steps of: a) forming a porous or dense low k dielectric layer on a substrate; b) forming single or dual damascene etched openings in the low k dielectric; c) placing the substrate in a process chamber on a cold chuck at a temperature about −200° C. to about 25° C.; d) adding to the process chamber a condensable cleaning agent (CCA) to condense a layer of CCA within the etched openings on the substrate; and e) performing an activation step while the wafer remains cold at a temperature of about −200° C. to about 25° C. The via contacts are very stable during thermal cycles and during operation of the semiconductor device.

摘要翻译： 提供了在具有多个通孔接触电阻低的半导体器件上制造BEOL互连结构的方法。 该方法包括以下步骤：a）在衬底上形成多孔或致密的低k电介质层; b）在低k电介质中形成单个或双镶嵌蚀刻开口; c）将基板放置在约-200℃至约25℃的温度下的冷卡盘上的处理室中; d）向处理室中加入可冷凝清洁剂（CCA），以在衬底上的蚀刻开口内冷凝CCA层; 以及e）当晶片在约-200℃至约25℃的温度下保持冷时，执行激活步骤。在热循环期间和在半导体器件的操作期间，通孔触点是非常稳定的。

公开(公告)号：US20050186778A1

公开(公告)日：2005-08-25

申请号：US11104764

申请日：2005-04-12

申请人： Donald Canaperi ,  Timothy Dalton ,  Stephen Gates ,  Mahadevaiyer Krishnan ,  Satya Nitta ,  Sampath Purushothaman ,  Sean Smith

发明人： Donald Canaperi ,  Timothy Dalton ,  Stephen Gates ,  Mahadevaiyer Krishnan ,  Satya Nitta ,  Sampath Purushothaman ,  Sean Smith

IPC分类号： H01L21/768 ,  H01L21/00 ,  H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less-robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.

摘要翻译： 一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能互连。 布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中布置非常低的k和较不稳定的间隙填充电介质，使得该结构将耐用层与强度非常相似 低k电介质用于互连电气性能。