Method of forming a silicon gate to produce silicon devices with
improved performance
    51.
    发明授权
    Method of forming a silicon gate to produce silicon devices with improved performance 失效
    形成硅栅极以产生具有改进性能的硅器件的方法

    公开(公告)号:US5981364A

    公开(公告)日:1999-11-09

    申请号:US568195

    申请日:1995-12-06

    IPC分类号: H01L21/28 H01L29/49

    CPC分类号: H01L21/28035 H01L29/4925

    摘要: Disclosed herein is a method of forming a silicon gate stack onto a silicon substrate for a silicon device. The method of forming the silicon gate stack comprises the steps of growing an oxide layer onto the silicon substrate, depositing a thin layer of silicon to form a thin layer of silicon over the oxide layer, depositing a thick layer of silicon over the thin layer of silicon, and introducing impurities into only the thick layer of silicon to form a silicon gate whereby the silicon gate includes the thin layer of silicon and the thick layer of silicon having the impurities. The impurities being introduced with a concentration, the impurities concentration and the thick layer thickness impeding an encroachment by the oxide layer into the silicon gate during application of a protective screen oxide layer around the silicon gate stack.

    摘要翻译: 本文公开了一种在硅器件的硅衬底上形成硅栅叠层的方法。 形成硅栅极堆叠的方法包括以下步骤:在硅衬底上生长氧化物层,沉积薄层的硅以在氧化物层上形成薄的硅层,在薄层上沉积厚的硅层 硅,并且将杂质引入仅硅的厚层中以形成硅栅极,由此硅栅极包括硅的薄层和具有杂质的厚的硅层。 引入浓度的杂质,杂质浓度和厚层厚度在施加硅栅堆叠周围的保护性屏蔽氧化物层时阻碍氧化层侵入硅栅中。

    Method of forming dual field isolation structures
    52.
    发明授权
    Method of forming dual field isolation structures 失效
    形成双场隔离结构的方法

    公开(公告)号:US5966618A

    公开(公告)日:1999-10-12

    申请号:US36288

    申请日:1998-03-06

    CPC分类号: H01L21/76221 H01L27/105

    摘要: A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.

    摘要翻译: 提供厚且薄的氧化物结构的方法减小了集成电路上的芯区域和周边区域之间的阶跃变化。 在闪速存储器件的核心区域中提供了薄的LOCOS结构,并且在闪速存储器件的外围区域中提供了厚的LOCOS结构。 设备和过程不容易受到“赛道”问题,“氧化物”碰撞问题和“纵梁”问题的影响。 该方法利用两个分开的氮化物或硬掩模层。

    Dual source side polysilicon select gate structure utilizing single
tunnel oxide for NAND array flash memory
    53.
    发明授权
    Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory 失效
    双源端多晶硅选择门结构利用单隧道氧化物用于NAND阵列闪存

    公开(公告)号:US5912489A

    公开(公告)日:1999-06-15

    申请号:US940674

    申请日:1997-09-30

    CPC分类号: G11C16/0483

    摘要: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

    摘要翻译: 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极,串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元,串联选择晶体管的栅极升高到Vcc,同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压,而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

    Vision based method for micromanipulating biological samples
    60.
    发明授权
    Vision based method for micromanipulating biological samples 有权
    用于微生物样品的基于视觉的方法

    公开(公告)号:US08846379B2

    公开(公告)日:2014-09-30

    申请号:US12933608

    申请日:2008-03-19

    申请人: Yu Sun Wenhui Wang

    发明人: Yu Sun Wenhui Wang

    IPC分类号: C12M1/36

    摘要: A system and method for micromanipulating samples are described to perform automatic, reliable, and high-throughput sample microinjection of foreign genetic materials, proteins, and other molecules, as well as drawing genetic materials, proteins, and other molecules from the sample. The system and method overcome the problems inherent in traditional manual micromanipulation that is characterized by poor reproducibility, human fatigue, and low throughput. The present invention is particularly suited for adherent cell microinjection but can be readily extended to aspiration, isolation, and electrophysiological measurements of microorganisms, unicellular organisms, or cells.

    摘要翻译: 描述了用于微操作样品的系统和方法,以执行外来遗传物质,蛋白质和其他分子的自动,可靠和高通量样品显微注射,以及从样品中绘制遗传物质,蛋白质和其他分子。 该系统和方法克服了传统手动显微操作中固有的问题,其特点是重现性差,人体疲劳,生产能力低。 本发明特别适用于粘附细胞显微注射,但可以容易地扩展到微生物,单细胞生物体或细胞的抽吸,分离和电生理学测量。