公开(公告)号：US12052863B2

公开(公告)日：2024-07-30

申请号：US16572926

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gurtej S. Sandhu ,  Kunal R. Parekh

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/30 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B99/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/30 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B99/00

Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

公开(公告)号：US20240176523A1

公开(公告)日：2024-05-30

申请号：US18516734

申请日：2023-11-21

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin ,  Ameen D. Akel

IPC: G06F3/06 ,  G06F1/06

CPC classification number: G06F3/064 ,  G06F1/06 ,  G06F3/061 ,  G06F3/0683

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of the circuitry configured to access the set of memory arrays, and a second die may include a second portion of the circuitry configured to access the set of memory arrays. The first portion and the second portion of the circuitry configured to access a set of memory arrays may be communicatively coupled between the dies using various interconnection techniques, such as a fusion of conductive contacts of the respective memory dies. In some examples, the second die may also include the host itself (e.g., a host processor).

公开(公告)号：US11996377B2

公开(公告)日：2024-05-28

申请号：US17364335

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh ,  Beau D. Barry

IPC: H01L25/065 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  G11C11/4085 ,  G11C11/4091 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US11978656B2

公开(公告)日：2024-05-07

申请号：US16983559

申请日：2020-08-03

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L21/265 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/498 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00 ,  H01L27/06

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L29/66568 ,  H01L29/78 ,  H10B12/485 ,  H01L27/0694 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H10B12/09

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US11937429B2

公开(公告)日：2024-03-19

申请号：US17556704

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/1157 ,  H01L23/528 ,  H01L23/532 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/528 ,  H01L23/53257 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US20240087987A1

公开(公告)日：2024-03-14

申请号：US18507721

申请日：2023-11-13

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Systems and methods for a semiconductor device having a front-end-of-line structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. The interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. The semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

公开(公告)号：US11915742B2

公开(公告)日：2024-02-27

申请号：US17885242

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kunal R. Parekh ,  Aliasger T. Zaidy ,  Glen E. Hush

IPC: G06F13/00 ,  G11C11/4093 ,  G06F13/16 ,  G06F3/06 ,  G11C11/4096 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L21/66 ,  H01L25/18 ,  H01L25/00 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G16B50/10 ,  G16B30/00 ,  G06F13/28

CPC classification number: G11C11/4093 ,  G06F3/0656 ,  G06F13/1673 ,  G06F13/28 ,  G11C7/08 ,  G11C7/1039 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/78 ,  H01L22/12 ,  H01L24/08 ,  H01L24/48 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  G06F2213/28 ,  H01L24/16 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/1601 ,  H01L2224/16221 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/14335

Abstract: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of a genetic sequence from the memory die and through a wafer-on-wafer bond. The logic die can also perform a genome annotation lotic operation to attach biological information to the genetic sequence. An annotated genetic sequence can be provided as an output.

公开(公告)号：US20240063205A1

公开(公告)日：2024-02-22

申请号：US18491702

申请日：2023-10-20

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/18 ,  H01L25/50 ,  H01L24/83 ,  H10B12/33 ,  H10B12/036 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L2224/83895 ,  H01L2224/83896

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.

公开(公告)号：US20240040775A1

公开(公告)日：2024-02-01

申请号：US18478031

申请日：2023-09-29

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh ,  Terrence B. McDaniel ,  Beau D. Barry

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/50 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/488

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US20230395159A1

公开(公告)日：2023-12-07

申请号：US18315311

申请日：2023-05-10

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Kunal R. Parekh ,  Hernan A. Castro

IPC: G11C16/24 ,  H10B43/40 ,  H10B43/10 ,  G11C16/16

CPC classification number: G11C16/24 ,  H10B43/40 ,  H10B43/10 ,  G11C16/16 ,  G11C16/0483

Abstract: Interfaces between higher voltage and lower voltage wafers and related apparatuses and methods are disclosed. An apparatus includes a memory wafer and a logic wafer. Data storage elements of an array are configured to perform an operation responsive to an operational voltage potential. The memory wafer also includes bitlines electrically connected to the data storage elements and isolation devices electrically connected to the bitlines. The logic wafer is bonded to the memory wafer. The logic wafer includes logic circuitry electrically connected to the bitlines through the isolation devices. A maximum voltage potential difference tolerance of the logic circuitry is less than an operational voltage potential difference between the operational voltage potential and a reference voltage potential of the logic circuitry. A method includes isolating the logic circuitry from the bitlines, applying the operational voltage potential the data storage elements, and electrically connecting the logic circuitry to the bitlines.