公开(公告)号：US20190035472A1

公开(公告)日：2019-01-31

申请号：US16148405

申请日：2018-10-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi ,  Toru Tanzawa

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/08 ,  G11C16/32 ,  G11C16/12

Abstract: Programming methods include programming first and second data in first and second memory cells, reading the first data from the first memory cell by applying a read voltage to an access line connected to the first and second memory cells while the first memory cell is electrically connected to a data line and while the second memory cell is electrically disconnected from the data line, reading the second data from the second memory cell by electrically disconnecting the first memory cell from the data line and electrically connecting the second memory cell to the data line while the read voltage remains applied to the access line, and programming the read first data and the read second data in a single memory cell connected to a different access line.

公开(公告)号：US10134478B2

公开(公告)日：2018-11-20

申请号：US15436289

申请日：2017-02-17

Applicant: Micron Technology, Inc.

Inventor： Feng Pan ,  Ramin Ghodsi ,  Qiang Tang

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16

Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

公开(公告)号：US20180191528A1

公开(公告)日：2018-07-05

申请号：US15904660

申请日：2018-02-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Xiaojiang Guo ,  Chang Wan Ha

IPC: H04L25/02 ,  G11C29/02 ,  G06F13/40 ,  G11C29/50 ,  G11C5/04

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  G11C5/04 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: Methods of operating integrated circuit devices include generating a voltage level at a particular node in response to a first voltage level applied to a termination device and a second voltage level applied to a reference resistance; determining whether a plurality of available resistance values of the termination device satisfy a criterion that each available resistance value is either less than a resistance value of the reference resistance, or each available resistance value is greater than the resistance value of the reference resistance; and, when the plurality of available resistance values of the termination device satisfy the criterion, determining whether a voltage level generated at the particular node for a particular available resistance value of the plurality of available resistance values is between a voltage level of a first reference voltage and a voltage level of a second reference voltage.

公开(公告)号：US20170352409A1

公开(公告)日：2017-12-07

申请号：US15687710

申请日：2017-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Xiaojiang Guo ,  Ramin Ghodsi

IPC: G11C11/56 ,  G06F12/02 ,  G11C16/12 ,  G11C16/04 ,  G06F3/06 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

Abstract: Methods of operating a memory device include applying a programming pulse to a plurality of memory cells selected for programming having an initial portion having a first voltage level and a subsequent portion having a second voltage level less than the first voltage level, inhibiting a particular memory cell of the plurality of memory cells from programming during the initial portion of the programming pulse while a different memory cell of the plurality of memory cells is enabled for programming, and inhibiting the different memory cell from programming during the subsequent portion of the programming pulse while the particular memory cell is enabled for programming.

公开(公告)号：US09659950B2

公开(公告)日：2017-05-23

申请号：US14877997

申请日：2015-10-08

Applicant: Micron Technology, Inc.

Inventor： Aaron Yip ,  Qiang Tang ,  Chang Wan Ha

IPC: H01L27/115 ,  H01L27/11556 ,  G11C16/06

CPC classification number: H01L27/11556 ,  G11C16/06 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.

公开(公告)号：US09607692B2

公开(公告)日：2017-03-28

申请号：US14868604

申请日：2015-09-29

Applicant: Micron Technology, Inc.

Inventor： Qiang Tang ,  Feng Pan ,  Ramin Ghodsi ,  Mark A. Helm

IPC: G11C11/34 ,  G11C16/06 ,  G11C11/56 ,  G11C7/14 ,  G11C29/02 ,  G11C29/04

CPC classification number: G11C11/5642 ,  G11C7/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.

公开(公告)号：US09552856B2

公开(公告)日：2017-01-24

申请号：US15095347

申请日：2016-04-11

Applicant: Micron Technology, Inc.

Inventor： Qiang Tang ,  Ramin Ghodsi

IPC: G11C7/22 ,  G11C11/4076 ,  G11C7/10 ,  G11C16/32 ,  G11C29/02 ,  G11C16/10 ,  G11C11/4093 ,  G11C29/04

CPC classification number: G11C7/22 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/10 ,  G11C16/32 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409

Abstract: Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. The data path can include a data latch coupled to the delay circuit. A clock is coupled to the data latch to clock data into the data latch. Transitions of the data are substantially aligned with transitions of the clock. An output of the data latch is read after each delay trim setting is programmed. A boundary is determined between a first output state of the data latch and a second output state of the data latch wherein the boundary is associated with a particular delay trim setting of the plurality of delay trim settings. The particular delay trim setting is programmed into the delay circuit.

Abstract translation: 公开了用于存储器输入定时自校准的方法，用于输入定时自校准的装置和系统。 一种这样的方法包括将多个延迟微调设置顺序地编程到数据路径的延迟电路中。 数据路径可以包括耦合到延迟电路的数据锁存器。 时钟耦合到数据锁存器，将数据时钟数据插入数据锁存器。 数据的转换基本上与时钟的转换对齐。 在对每个延迟微调设置进行编程后，读取数据锁存器的输出。 在数据锁存器的第一输出状态和数据锁存器的第二输出状态之间确定边界，其中边界与多个延迟调整设置的特定延迟微调设置相关联。 特定的延迟调整设置被编程到延迟电路中。

公开(公告)号：US09460803B1

公开(公告)日：2016-10-04

申请号：US14864990

申请日：2015-09-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Eric N. Lee ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C5/063 ,  G11C7/04 ,  G11C7/08 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/32

Abstract: A system includes a plurality of sensing devices, a first multiplexer, a plurality of local return clock signal paths, a second multiplexer, and a data latch. Each sensing device outputs data onto a respective local data path in response to a clock signal on a clock signal path. The first multiplexor passes data from a selected local data path to a global data path. Each local return clock signal path is coupled to the clock signal path at a respective sensing device such that each local return clock signal path is routed along with a respective local data path. The second multiplexor passes a return clock signal from a selected local return clock signal path corresponding to the selected local data path to a global return clock signal path. The data latch latches the data on the global data path into the data latch in response to the return clock signal on the global return clock signal path.

Abstract translation: 系统包括多个感测装置，第一多路复用器，多个本地返回时钟信号路径，第二多路复用器和数据锁存器。 每个感测装置响应于时钟信号路径上的时钟信号将数据输出到相应的本地数据路径上。 第一多路复用器将数据从选定的本地数据路径传递到全局数据路径。 每个本地返回时钟信号路径在相应感测装置处耦合到时钟信号路径，使得每个本地返回时钟信号路径与相应的本地数据路径一起路由。 第二多路复用器将来自对应于所选择的本地数据路径的选择的本地返回时钟信号路径的返回时钟信号传递到全局返回时钟信号路径。 响应于全局返回时钟信号路径上的返回时钟信号，数据锁存器将全局数据通路上的数据锁存到数据锁存器中。

公开(公告)号：US20160274614A1

公开(公告)日：2016-09-22

申请号：US14661706

申请日：2015-03-18

Applicant: Micron Technology, Inc.

Inventor： Qiang Tang ,  Ruo-Gu Huang ,  Xiaojiang Guo

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: Generally discussed herein are apparatuses and methods for a voltage regulator with a current feedback loop. One such apparatus may include an amplifier, a master device electrically coupled to the amplifier, a slave device electrically coupled to the master device, and/or a current feedback device electrically coupled to the amplifier and the slave device to feed back current from the slave device to alter a monitoring voltage input to the amplifier.

Abstract translation: 这里通常讨论的是具有电流反馈回路的电压调节器的装置和方法。 一种这样的设备可以包括放大器，电耦合到放大器的主设备，电耦合到主设备的从设备和/或电耦合到放大器和从设备的电流反馈设备，以从从设备反馈电流 用于改变输入到放大器的监控电压的装置。

公开(公告)号：US09368212B1

公开(公告)日：2016-06-14

申请号：US14669705

申请日：2015-03-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Qiang Tang

IPC: G11C19/08 ,  G11C16/06 ,  G11C29/12

CPC classification number: G11C16/06 ,  G11C7/04 ,  G11C8/08 ,  G11C16/08 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/50004 ,  G11C2029/1202 ,  G11C2029/5002

Abstract: A device includes an array of memory cells, a temperature sensor to provide a temperature output, and a circuit. The circuit provides a bias voltage to bias a node of the array of memory cells based on the temperature output, a first voltage component independent of a temperature coefficient of the memory cells, and a second voltage component dependent on the temperature coefficient of the memory cells. The first voltage component is determined at a first temperature and the second voltage component is determined at a second temperature less than the first temperature.

Abstract translation: 一种器件包括存储器单元阵列，用于提供温度输出的温度传感器和电路。 该电路提供偏置电压以基于温度输出偏置存储器单元阵列的节点，独立于存储器单元的温度系数的第一电压分量，以及取决于存储器单元的温度系数的第二电压分量 。 在第一温度下确定第一电压分量，并且在小于第一温度的第二温度下确定第二电压分量。