公开(公告)号：US08886481B1

公开(公告)日：2014-11-11

申请号：US12835184

申请日：2010-07-13

申请人： Arifur Rahman ,  Michael J. Hart ,  Venkatesan Murali

发明人： Arifur Rahman ,  Michael J. Hart ,  Venkatesan Murali

IPC分类号： G06F19/00

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A method of reducing variation in multi-die integrated circuits can include, for each of a plurality of dies, determining at least one performance metric and selecting at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric. Systems and devices for executing the steps of the method are also described.

摘要翻译： 减少多管芯集成电路中的变化的方法可以包括对于多个管芯中的每一个，确定至少一个性能度量并且根据至少一个性能选择至少两个管芯以包括在多管芯集成电路内 度量。 还描述了用于执行该方法的步骤的系统和设备。

公开(公告)号：US08802454B1

公开(公告)日：2014-08-12

申请号：US13331702

申请日：2011-12-20

申请人： Arifur Rahman ,  Henley Liu ,  Cheang-Whang Chang ,  Myongseob Kim ,  Dong W. Kim

发明人： Arifur Rahman ,  Henley Liu ,  Cheang-Whang Chang ,  Myongseob Kim ,  Dong W. Kim

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L22/14

摘要： A method for testing TSVs is provided. A plurality of TSVs is formed in a semiconductor substrate. Wiring layers and a first contact array are formed on the front-side of the substrate. The wiring layers couple each of the TSVs to a respective contact of the first contact array. Conductive adhesive is deposited over the first contact array. The conductive adhesive electrically couples contacts of the first contact array. A carrier is bonded to the front-side of the substrate with the conductive adhesive. After bonding the carrier to the substrate, the back-side of the substrate is thinned to expose each of the TSVs on the back-side of the substrate. A second contact array is formed, having a contact coupled to each respective TSV. Conductivity and connections of the TSVs, wiring layers, and contacts are tested by testing for conductivity between contacts of the second contact array.

摘要翻译： 提供了一种测试TSV的方法。 在半导体衬底中形成多个TSV。 布线层和第一接触阵列形成在基板的正面上。 布线层将每个TSV耦合到第一接触阵列的相应触头。 导电胶粘剂沉积在第一接触阵列上。 导电粘合剂电耦合第一接触阵列的触点。 载体用导电粘合剂粘合到基底的正面。 在将载体接合到基板之后，将基板的背面变薄以使基板的背面上的每个TSV露出。 形成第二接触阵列，其具有耦合到每个相应TSV的接触。 通过测试第二接触阵列的触头之间的电导率来测试TSV，布线层和触点的电导率和连接。

公开(公告)号：US08546191B2

公开(公告)日：2013-10-01

申请号：US12958309

申请日：2010-12-01

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H01L21/60

CPC分类号： H01L21/563 ,  H01L23/544 ,  H01L25/0655 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/73203

摘要： In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice is mounted on a semiconductor substrate, and neighboring ones of the dice are separated by a distance at which a first one of the neighboring dice will contact a meniscus of a flange of the neighboring die during underfill to form a capillary bridge between the neighboring dice. Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact terminals on a top surface of the substrate. Underfill is deposited along one or more edges of one or more of the plurality of dice. As a result of the capillary bridge formed between neighboring dice, flow of underfill is induced between the bottom surfaces of the neighboring dice and the top surface of the substrate. The dispensed underfill is cured.

摘要翻译： 在一个实施例中，提供了一种形成多芯片半导体器件的方法。 多个骰子安装在半导体衬底上，并且相邻骰子之间的相邻骰子被分开一段距离，在该距离处，相邻骰子中的第一个骰子将在底部填充期间与邻近骰子的凸缘的弯液面接触，以形成毛细管桥， 相邻的骰子。 焊接凸块被回流以将多个裸片的接触端子电连接到衬底的顶表面上的接触端子。 底部填充物沉积在多个骰子中的一个或多个骰子的一个或多个边缘上。 作为在相邻骰子之间形成的毛细管桥的结果，在相邻骰子的底表面和衬底的顶表面之间引起底部填充物的流动。 分配的底部填充物固化。

公开(公告)号：US08296689B1

公开(公告)日：2012-10-23

申请号：US12419234

申请日：2009-04-06

申请人： Arifur Rahman ,  Hong-tsz Pan

发明人： Arifur Rahman ,  Hong-tsz Pan

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： Method, apparatus, and computer readable medium for designing an integrated circuit (IC) are described. In some examples, layout data describing conductive layers of the integrated circuit is obtained. The layout data is analyzed to identify through die via (TDV) areas. A metal fill pattern is created for each of the TDV areas having a maximum metal density within design rules for the integrated circuit. The metal fill pattern for each of the TDV areas is merged with the layout data.

摘要翻译： 描述了用于设计集成电路（IC）的方法，装置和计算机可读介质。 在一些示例中，获得了描述集成电路的导电层的布局数据。 分析布局数据，以便通过（TDV）区域识别。 为集成电路的设计规则中具有最大金属密度的每个TDV区域创建金属填充图案。 每个TDV区域的金属填充图案与布局数据合并。

公开(公告)号：US08237274B1

公开(公告)日：2012-08-07

申请号：US12779806

申请日：2010-05-13

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC分类号： H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/06051 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13023 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17107 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A semiconductor device is provided that includes a substrate having opposing first and second surfaces and an interconnect structure extending between the first and second surfaces. A plurality of bond pads are located on the first surface of the substrate and the bond pads are electrically connected to the interconnect structure. The bond pads each have two or more micro-bumps, with the two or more micro-bumps on each bond pad being arranged to electrically connect the bond pad to one die pad of a semiconductor die. A plurality of external contacts are located on the second surface of the substrate and the external contacts are electrically connected to the interconnect structure.

摘要翻译： 提供一种半导体器件，其包括具有相对的第一和第二表面的基板和在第一和第二表面之间延伸的互连结构。 多个接合焊盘位于衬底的第一表面上，并且接合焊盘电连接到互连结构。 接合焊盘各自具有两个或更多个微凸块，每个接合焊盘上的两个或更多个微凸块被布置成将接合焊盘电连接到半导体管芯的一个管芯焊盘。 多个外部触点位于基板的第二表面上，并且外部触头电连接到互连结构。

公开(公告)号：US08156456B1

公开(公告)日：2012-04-10

申请号：US12829213

申请日：2010-07-01

申请人： Arifur Rahman ,  Min-Hsing Chen

发明人： Arifur Rahman ,  Min-Hsing Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/74

摘要： A method of designing an integrated circuit (IC) having multiple dies can include identifying a unified design library having a first process node specific (PNS) library for a first IC process technology and a second PNS library for a second IC process technology. The first PNS library can be correlated with a first die of the IC. The second PNS library can be correlated with the second die of the IC. Via a processor, a circuit element can be defined within a circuit design implemented within the IC according to the PNS library correlated to the die in which the circuit element is located.

摘要翻译： 设计具有多个管芯的集成电路（IC）的方法可以包括识别具有用于第一IC工艺技术的第一工艺节点特定（PNS）库和用于第二IC工艺技术的第二PNS库的统一设计库。 第一个PNS库可以与IC的第一个管芯相关联。 第二个PNS库可以与IC的第二个管芯相关联。 通过处理器，可以根据与电路元件所在的管芯相关联的PNS库，在IC内实现的电路设计中定义电路元件。

公开(公告)号：US08089299B1

公开(公告)日：2012-01-03

申请号：US12436918

申请日：2009-05-07

申请人： Arifur Rahman ,  Bernard J. New

发明人： Arifur Rahman ,  Bernard J. New

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： An integrated circuit die is described that includes an array of tiles arranged in columns. The integrated circuit die includes interface tiles having at least one row of through die vias. The integrated circuit die includes metal layers that include horizontal wiring tracks and metal layers that include vertical wiring tracks. At least some of the metal layers having vertical wiring segments include horizontal wiring segments. Each horizontal wiring segment is coupled to a first wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias and is coupled to a second wiring segment of the horizontal wiring track that is interrupted by the at least one row of through die vias. Each horizontal wiring segment extends between the at least one row of through die vias and at least one row of through die vias in an adjoining interface tile.

摘要翻译： 描述了一种集成电路管芯，其包括以列排列的瓦片阵列。 集成电路管芯包括具有至少一排通孔的界面砖。 集成电路管芯包括包括水平布线轨道和包括垂直布线轨道的金属层的金属层。 具有垂直布线段的至少一些金属层包括水平布线段。 每个水平布线段耦合到水平布线轨道的第一布线段，该第一布线段由至少一行贯通管道通孔中断，并且连接到由至少一个中断的水平布线轨道的第二布线段 一排穿过通孔。 每个水平布线段在至少一排通孔通孔之间延伸，并且在邻接的界面砖中延伸至少一排通孔。

公开(公告)号：US20110316572A1

公开(公告)日：2011-12-29

申请号：US12824536

申请日：2010-06-28

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G01R31/02 ,  H01L23/58 ,  G01R31/20 ,  G01R31/26

CPC分类号： G01R31/318513 ,  G01R31/2853 ,  H01L22/14 ,  H01L22/20 ,  H01L22/22 ,  H01L22/32 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157

摘要： A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections.

摘要翻译： 测试多芯片集成电路（IC）的方法可以包括测试多芯片IC的管芯间连接。 管芯间连接可以包括将第一管芯耦合到第二管芯的微突起。 该方法可以包括在芯片间连接的测试期间检测故障是否发生。 响应于检测故障，多芯片集成电路可以被指定为包括故障的管芯间连接。 还描述了一种集成电路，其包括第一管芯，可以设置第一管芯的第二管芯，将第一管芯耦合到第二管芯的多个管芯间连接，以及多个探针焊盘，其中每个探针 焊盘耦合到至少一个管芯间连接。

公开(公告)号：US07968375B1

公开(公告)日：2011-06-28

申请号：US12540991

申请日：2009-08-13

申请人： Arifur Rahman ,  Stephen M. Trimberger

发明人： Arifur Rahman ,  Stephen M. Trimberger

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L23/642 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19103 ,  H01L2924/00014

摘要： Method and apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.

摘要翻译： 描述了在堆叠集成电路中集成电容器的方法和装置。 本发明的一个方面涉及一种具有载体衬底，多个集成电路芯片和至少一种金属 - 绝缘体 - 金属（MIM）电容器的半导体组件。 集成电路芯片垂直堆叠在载体基板上。 每个MIM电容器设置在多个集成电路芯片的第一集成电路管芯和第二集成电路管芯之间。 所述至少一个MIM电容器被制造在所述第一集成电路管芯的表面和所述第二集成电路管芯的背面中的至少一个上。

公开(公告)号：US07930661B1

公开(公告)日：2011-04-19

申请号：US12185511

申请日：2008-08-04

申请人： Stephen M. Trimberger ,  Arifur Rahman ,  Bernard J. New

发明人： Stephen M. Trimberger ,  Arifur Rahman ,  Bernard J. New

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A software model (620) of a stacked integrated circuit system (600) includes a first integrated circuit die (602) connected to a second integrated circuit die (604) through an interchip communication interface (606). A software model of the first integrated circuit die includes an integrated circuit resource (614) and an internal interface (150). A software model of the second integrated circuit die includes a stacked resource (618). The software model of the internal interface is configurable to connect the stacked resource of the second integrated circuit die to the integrated circuit resource through the interchip communication interface.

摘要翻译： 层叠集成电路系统（600）的软件模型（620）包括通过芯片间通信接口（606）连接到第二集成电路管芯（604）的第一集成电路管芯（602）。 第一集成电路管芯的软件模型包括集成电路资源（614）和内部接口（150）。 第二集成电路管芯的软件模型包括堆叠资源（618）。 内部接口的软件模型可配置为通过芯片间通信接口将第二个集成电路管芯的堆叠资源连接到集成电路资源。