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    Nonvolatile memory device with on-die control and data signal termination
    51.
    发明授权
    Nonvolatile memory device with on-die control and data signal termination 有权
    具有片上控制和数据信号终止的非易失性存储器件

    公开(公告)号：US09306564B2

    公开(公告)日：2016-04-05

    申请号：US14695260

    申请日：2015-04-24

    Applicant: Rambus Inc.

    Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

    IPC: H03K17/16 ,  H03K19/00 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  G11C11/419 ,  G11C16/26 ,  G11C11/41 ,  G11C11/4063 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G11C16/32

    CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

    Abstract: In a non-volatile memory device having an array of non-volatile storage elements, control information received via one or more control input nodes indicates, at different times, that (i) data signals representative of data to be stored within the array of non-volatile storage elements are to be received via a plurality of input/output (I/O) nodes of the non-volatile memory device, and (ii) data signals representative of data read from the array of non-volatile storage elements are to be output via the plurality of I/O nodes. First termination elements are switchably coupled to and decoupled from the I/O nodes based at least in part on the control information, and second termination elements are switchably coupled to and decoupled from the one or more control input nodes based at least in part on the control information.

    Abstract translation: 在具有非易失性存储元件的阵列的非易失性存储器件中，经由一个或多个控制输入节点接收的控制信息在不同时间指示（i）表示要存储在非阵列阵列内的数据的数据信号， 非挥发性存储元件将通过非易失性存储器件的多个输入/输出（I / O）节点接收，并且（ii）代表从非易失性存储元件阵列读取的数据的数据信号是 通过多个I / O节点输出。 至少部分地基于控制信息，第一终端元件可切换地耦合到I / O节点并从I / O节点去耦，并且第二终端元件至少部分地基于控制信息而切换地耦合到一个或多个控制输入节点并从该一个或多个控制输入节点去耦 控制信息。

    Reducing Unwanted Reflections in Source-Terminated Channels
    54.
    发明申请
    Reducing Unwanted Reflections in Source-Terminated Channels 有权
    减少源终止渠道的不必要的反思

    公开(公告)号：US20150205751A1

    公开(公告)日：2015-07-23

    申请号：US14411723

    申请日：2013-07-17

    Applicant: Rambus Inc.

    Inventor： Kyung Suk Oh ,  Pravin Kumar Venkatesan ,  Yohan Usthavia Frans

    IPC: G06F13/42 ,  G06F13/28

    CPC classification number: G06F13/4221 ,  G06F13/28 ,  H04L25/0278 ,  H04L25/0298 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A memory controller and/or memory device control termination of a communication link in order to achieve power savings while reducing or eliminating unwanted reflections in the channel. Following transmission of data over the communication channel, termination is left enabled for a programmable time period beginning immediately following completion of the transmission. The time period is sufficiently long to allow the unwanted reflections to be absorbed by the termination. Following the time period, the termination is disabled for power savings.

    Abstract translation: 存储器控制器和/或存储器设备控制通信链路的终端，以便在减少或消除信道中的不必要的反射的同时实现功率节省。 在通过通信信道传输数据之后，在传输完成之后立即开始可编程时间段的终止。 该时间段足够长以允许不期望的反射被终端吸收。 在该时间段之后，终止功能被禁用以节省电力。

    On-Die Termination of Address and Command Signals
    55.
    发明申请
    On-Die Termination of Address and Command Signals 有权
    地址和命令信号的终止

    公开(公告)号：US20150170724A1

    公开(公告)日：2015-06-18

    申请号：US14613270

    申请日：2015-02-03

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Kyung Suk Oh

    IPC: G11C7/22

    CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

    Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

    Abstract translation: 系统具有以飞越拓扑布置的多个存储器件，每个存储器件具有用于连接到地址和控制（RQ）总线的片上终端（ODT）电路。 每个存储器件的ODT电路包括一组一个或多个控制寄存器，用于控制RQ总线的一个或多个信号线的管芯端接。 第一存储器件包括存储第一ODT值的一个或多个控制寄存器的第一组，用于控制由第一存储器件的ODT电路终止RQ总线的一个或多个信号线，第二存储器器件包括： 存储与第一ODT值不同的第二ODT值的一个或多个控制寄存器的第二组，用于控制由第二存储器件的ODT电路终止RQ总线的一个或多个信号线。

    Power saving driver design
    57.
    发明授权
    Power saving driver design 有权
    省电驱动设计

    公开(公告)号：US08922245B2

    公开(公告)日：2014-12-30

    申请号：US13963122

    申请日：2013-08-09

    Applicant: Rambus Inc.

    Inventor： Kyung Suk Oh ,  Chi-Ming Yeung ,  David A. Secker

    IPC: H03K3/012 ,  G11C7/10 ,  H04L25/02 ,  G11C11/4074

    CPC classification number: H03K3/012 ,  G11C7/1057 ,  G11C11/4074 ,  H04L25/028

    Abstract: In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the same value. The adjustment of the power consumed is performed on the bit value that consumes the most DC power and the other value is typically not adjusted.

    Abstract translation: 在不对称端接的通信系统中，基于输出位是否是具有相同值的第二，第三，第四等等的连续位，在输出特定位值之后，调整发送特定位值所消耗的功率 。 可以通过在具有相同值的第二个或后续的连续位中调整驱动器强度来进行用于传送具有相同值的两个或更多个连续位的消耗的功率的调整。 消耗功率的调整是对消耗最多DC功率的比特值进行的，另一个值通常不被调整。

    On-Die Termination of Address and Command Signals
    58.
    发明申请
    On-Die Termination of Address and Command Signals 有权
    地址和命令信号的终止

    公开(公告)号：US20140112084A1

    公开(公告)日：2014-04-24

    申请号：US14088277

    申请日：2013-11-22

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Kyung Suk Oh

    IPC: G11C11/4063

    CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

    Abstract: A memory controller is disclosed. The memory controller is configured to be connected to one or more memory devices via an address and control (RQ) bus. Each of the memory devices have on-die termination (ODT) circuitry connected to a subset of signal lines of the RQ bus, and the memory controller is operable to selectively disable the ODT circuitry in at least one memory device of the one or more memory devices.

    Abstract translation: 公开了一种存储器控制器。 存储器控制器被配置为经由地址和控制（RQ）总线连接到一个或多个存储器件。 每个存储器件具有连接到RQ总线的信号线子集的片上终端（ODT）电路，并且存储器控制器可操作地选择性地禁用该一个或多个存储器的至少一个存储器件中的ODT电路 设备。

    STRUCTURE FOR DELIVERING POWER
    59.
    发明公开
    STRUCTURE FOR DELIVERING POWER 审中-公开

    公开(公告)号：US20240215149A1

    公开(公告)日：2024-06-27

    申请号：US18535775

    申请日：2023-12-11

    Applicant: Rambus Inc.

    Inventor： Kyung Suk Oh ,  Ralf M. Schmitt ,  Yijong Feng

    IPC: H05K1/02 ,  H01B5/02 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H05K1/0216 ,  H01B5/02 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/5223 ,  H01L2924/0002

    Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

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