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    Method and apparatus for a lateral flux capacitor
    51.
    发明授权
    Method and apparatus for a lateral flux capacitor 失效
    横向磁通电容器的方法和装置

    公开(公告)号：US6028990A

    公开(公告)日：2000-02-22

    申请号：US222259

    申请日：1998-12-28

    申请人： Arvin R. Shahani ,  Thomas H. Lee ,  Hirad Samavati ,  Derek K. Shaeffer ,  Steven Walther

    发明人： Arvin R. Shahani ,  Thomas H. Lee ,  Hirad Samavati ,  Derek K. Shaeffer ,  Steven Walther

    IPC分类号： H01L27/08 ,  G06F17/50 ,  H01L27/105

    CPC分类号： H01L27/0805 ,  H01L28/86

    摘要： Linear integrated circuit capacitors having greater capacitance per unit area by using lateral flux. One embodiment comprises a two metal layer capacitor wherein each metal layer is comprised of two capacitor conductive components. The capacitor conductive components are cross-coupled so that the total capacitance is the sum of the vertical flux between the metal layers, and the lateral flux along the edges between the two capacitor conductive components in each of the metal layers. The lateral flux between the capacitor conductive components in a single metal layer increases the capacitance per unit area and decreases the bottom-plate parasitic capacitance. Increasing the length of the common edge formed by capacitor conductive components in a metal layer increases the capacitance per unit area. In one lateral flux capacitor, each metal layer is comprised of a plurality of rows, alternate rows are coupled together such that lateral flux is generated between each of the rows. The rows are also cross-coupled with rows in adjacent metal layers to provide vertical flux. Fractal shapes can be used to maximize the length of the perimeter of adjacent capacitor conductive components in a single metal layer. The Koch Islands and Minkowski Sausage families of fractals are particularly well suited for generating capacitor conductive component perimeter shapes. These fractals are generated by selecting an initiator shape and repeatedly applying a generator. The fractal shapes are generated by a computer program based upon user input parameters.

    摘要翻译： 线性集成电路电容器通过使用横向通量具有更大的电容单位面积。 一个实施例包括两个金属层电容器，其中每个金属层由两个电容器导电部件组成。 电容器导电部件被交叉耦合，使得总电容是金属层之间的垂直通量和沿着每个金属层中的两个电容器导电部件之间的边缘的横向磁通的总和。 单个金属层中的电容器导电元件之间的横向通量增加了每单位面积的电容，并降低了底板寄生电容。 增加由金属层中的电容器导电部件形成的共同边缘的长度增加了每单位面积的电容。 在一个横向通量电容器中，每个金属层由多个行组成，交替的行耦合在一起，使得在每行之间产生横向通量。 这些行还与相邻金属层中的行交叉耦合以提供垂直通量。 可以使用分形来最大化单个金属层中相邻电容器导电组件的周长的长度。 科赫群岛和明科夫斯基香肠分形系列特别适用于生成电容器导电组件周边形状。 这些分形是通过选择引发器形状并重复应用发生器来生成的。 基于用户输入参数的计算机程序生成分形。

    Differential charge pump circuit with high differential impedance and low common mode impedance
    52.
    发明授权
    Differential charge pump circuit with high differential impedance and low common mode impedance 失效
    差分电荷泵电路具有高差分阻抗和低共模阻抗

    公开(公告)号：US5736892A

    公开(公告)日：1998-04-07

    申请号：US415602

    申请日：1995-04-03

    申请人： Thomas H. Lee

    发明人： Thomas H. Lee

    IPC分类号： H03F3/45 ,  H03L7/093 ,  H03K17/56

    CPC分类号： H03F3/45179 ,  H03F3/45076 ,  H03F3/45183 ,  H03F2203/45176 ,  H03F2203/45188 ,  H03F2203/45201 ,  H03F2203/45208 ,  H03F2203/45466 ,  H03F2203/45644 ,  H03F2203/45674 ,  H03F2203/45712

    摘要： A high gain, low voltage differential amplifier exhibiting extremely low common mode sensitivities includes a load element exhibiting a high differential resistance, but a low common mode resistance. The load element contains a positive differential load resistance and a negative differential load resistance, which offsets the positive differential load resistance. The output common mode level of the differential amplifier is one p-channel source to gate voltage drop below the power supply voltage prohibiting the common mode output voltage from drifting far from an active level. The differential amplifier also has application for use in a differential charge pump circuit. The high differential impedance of the differential amplifier allows the attainment of extremely small leakage, while a low common-mode impedance results in simplified biasing.

    摘要翻译： 具有非常低的共模灵敏度的高增益低电压差分放大器包括具有高差分电阻但是具有低共模电阻的负载元件。 负载元件包含正差分负载电阻和负差分负载电阻，抵消正差分负载电阻。 差分放大器的输出共模电平是一个p沟道源极到栅极电压降低于电源电压，禁止共模输出电压远离有源电平漂移。 差分放大器也可应用于差分电荷泵电路。 差分放大器的高差分阻抗允许实现极小的泄漏，而低共模阻抗导致简化的偏置。

    Delay-locked loop
    53.
    发明授权
    Delay-locked loop 失效
    延迟锁定环路

    公开(公告)号：US5614855A

    公开(公告)日：1997-03-25

    申请号：US512597

    申请日：1995-08-21

    申请人： Thomas H. Lee ,  Kevin S. Donnelly ,  Tsyr-Chyang Ho ,  Mark G. Johnson

    发明人： Thomas H. Lee ,  Kevin S. Donnelly ,  Tsyr-Chyang Ho ,  Mark G. Johnson

    IPC分类号： G01R31/28 ,  H03L7/00 ,  H03L7/08 ,  H03L7/081 ,  H03L7/093 ,  H03K5/13

    CPC分类号： H03L7/0812

    摘要： A delay locked loop (DLL) is described in which a phase detector compares the phase of the output of the DLL with that of a reference input. The output of the phase comparator drives a differential charge pump which functions to integrate the phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used. For example, when a data receiver is used as the phase detector in the DLL, the output of the DLL is a clock signal which can be used as a sampling clock for data receivers elsewhere in the system, and is timed to sample data at the optional instant independent of temperature, supply voltage and process variations. Alternatively, a quadrature phase detector may be employed to generate a clock signal that possesses a quadrature (90.degree. ) relationship with a reference clock signal input. This may be used, for example, to generate a transmit clock for a data transmission device. Furthermore, the DLL is controlled to minimize dither jitter while minimizing acquisition time. In addition, duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, for example 50%. Additionally, the inputs to the charge pump are reversed in alternate quadrants of the phase plane in order to enable unlimited phase shift with a finite control voltage range.

    摘要翻译： 描述了延迟锁定环（DLL），其中相位检测器将DLL的输出的相位与参考输入的相位进行比较。 相位比较器的输出驱动一个差分电荷泵，用于对相位比较器输出信号随时间进行积分。 电荷泵输出控制无限幅度的移相器，可调节DLL输出的相位，使相位比较器的输出平均高达50％的时间。 因为DLL调整移相器，直到相位检测器的输出高达50％的时间，平均而言，DLL输出时钟与输入参考时钟的关系仅取决于所使用的相位检测器的类型。 例如，当数据接收器用作DLL中的相位检测器时，DLL的输出是可以用作系统中其他地方的数据接收器的采样时钟的时钟信号，并且被定时以在 可选速度独立于温度，电源电压和工艺变化。 或者，可以采用正交相位检测器来产生与参考时钟信号输入具有正交（90°）关系的时钟信号。 这可以用于例如为数据传输设备产生传输时钟。 此外，DLL被控制以最小化抖动抖动，同时最小化采集时间。 此外，采用占空比校正放大器来产生具有期望占空比的DLL输出时钟，例如50％。 此外，电荷泵的输入在相平面的交替象限中反转，以便在有限的控制电压范围内实现无限相移。

    Tendon stripper
    58.
    发明授权
    Tendon stripper 失效
    Tendon剥离器

    公开(公告)号：US07320687B2

    公开(公告)日：2008-01-22

    申请号：US11121747

    申请日：2005-05-04

    申请人： Thomas H. Lee

    发明人： Thomas H. Lee

    IPC分类号： A61B17/56

    CPC分类号： A61B17/32075 ,  A61B17/00008 ,  A61B17/32053 ,  A61B18/08

    摘要： The invention includes a tendon stripper comprising: (a) a frame, including a cautery, that is adapted to separate surrounding tissue along a length of a tendon; (b) a handle mounted to the frame that is adapted to reposition the frame with respect to the tendon; and (c) an actuator in communication with the cautery and operative to activate the cautery, where activation of the cautery is adapted to sever the tendon. The invention also includes a method of stripping a tendon comprising: (a) exposing a tendon; (b) aligning a tendon stripper guide with respect to a first location to the tendon; (c) repositioning the tendon stripper guide along the tendon from the first location of the tendon to a second location of the tendon, where the act of repositioning of the tendon stripper guide is operative to separate surrounding tissue from the tendon between the first location and the second location; (d) activating a cautery to sever the tendon approximate the second location; and (e) cutting the tendon at a location other than the second location to provide a tendon segment.

    摘要翻译： 本发明包括一种腱剥离器，其包括：（a）包括灼烧器的框架，其适于沿着腱的长度分离周围的组织; （b）安装到框架上的手柄，其适于相对于腱重新定位框架; 和（c）与所述灼烧器连通并且可操作地致动所述烧灼的致动器，其中所述烧灼的激活适于切断所述腱。 本发明还包括一种剥离腱的方法，包括：（a）暴露肌腱; （b）将腱剥离器引导件相对于腱的第一位置对准; （c）将腱剥离器引导件沿着腱从肌腱的第一位置重新定位到腱的第二位置，其中重新定位腱剥离器引导件的动作用于将周围组织与腱的第一位置和 第二个位置; （d）激活灼伤以切断腱近似第二位置; 和（e）在除了第二位置之外的位置处切割肌腱以提供腱段。

    Delay locked loop circuitry for clock delay adjustment
    59.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 失效
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US07039147B2

    公开(公告)日：2006-05-02

    申请号：US10366865

    申请日：2003-02-14

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H03D3/24

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟的数量，输入和输出时钟之间的不同相位关系是可能的。