公开(公告)号：US07148715B2

公开(公告)日：2006-12-12

申请号：US10860699

申请日：2004-06-02

申请人： Salman Akram ,  William M. Hiatt ,  Alan G. Wood ,  Charles M. Watkins ,  Kyle K. Kirby

发明人： Salman Akram ,  William M. Hiatt ,  Alan G. Wood ,  Charles M. Watkins ,  Kyle K. Kirby

IPC分类号： G01R31/02 ,  G01R31/26 ,  H01L27/00

CPC分类号： G01R31/2635 ,  G01R31/2831

摘要： Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.

公开(公告)号：US08294273B2

公开(公告)日：2012-10-23

申请号：US12985570

申请日：2011-01-06

申请人： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

发明人： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

摘要翻译： 用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。 通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。 通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。 可以在每个通孔的表面上形成阻挡层。 可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。 还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

公开(公告)号：US20110095429A1

公开(公告)日：2011-04-28

申请号：US12985570

申请日：2011-01-06

申请人： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

发明人： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

IPC分类号： H01L23/48 ,  H01L23/532

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

摘要： Methods for forming conductive vias include foiling one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof A barrier layer may be fowled over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

摘要翻译： 用于形成导电通孔的方法包括在基板中形成一个或多个通孔。 通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。 通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。阻挡层可以在每个通孔的表面上被覆盖。 可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。 还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

公开(公告)号：US07892972B2

公开(公告)日：2011-02-22

申请号：US11347153

申请日：2006-02-03

申请人： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

发明人： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

摘要翻译： 用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。 通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。 通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。 可以在每个通孔的表面上形成阻挡层。 可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。 还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

公开(公告)号：US07391117B2

公开(公告)日：2008-06-24

申请号：US11347930

申请日：2006-02-06

申请人： Kyle K. Kirby ,  Warren M. Farnworth

发明人： Kyle K. Kirby ,  Warren M. Farnworth

IPC分类号： H01L23/12

CPC分类号： G01R1/06733 ,  B33Y70/00 ,  B33Y80/00 ,  G01R1/06711 ,  G01R1/07314 ,  G01R3/00 ,  H01L23/49811 ,  H01L24/72 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/326 ,  H05K3/4092 ,  H01L2924/00 ,  H01L2224/05599

摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.

摘要翻译： 用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。 每个互连触点包括形成为导电弹簧元件的柔性导电层。 此外，柔性导电层包括用于接合部件触头的尖端和用于弹性地支撑尖端的弹簧部分部分。 一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。 成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。 导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。 互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。

公开(公告)号：US08503156B2

公开(公告)日：2013-08-06

申请号：US13169915

申请日：2011-06-27

申请人： Dewali Ray ,  Warren M. Farnworth ,  Kyle K. Kirby

发明人： Dewali Ray ,  Warren M. Farnworth ,  Kyle K. Kirby

IPC分类号： H01L21/683

CPC分类号： H01L21/6833

摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.

公开(公告)号：US07989022B2

公开(公告)日：2011-08-02

申请号：US11780628

申请日：2007-07-20

申请人： Dewali Ray ,  Warren M. Farnworth ,  Kyle K. Kirby

发明人： Dewali Ray ,  Warren M. Farnworth ,  Kyle K. Kirby

IPC分类号： C23C16/00

CPC分类号： H01L21/6833

摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.

摘要翻译： 处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。 导体从物理接触暴露的导电电极去除。 电介质材料施加在导电电极上。 在静电接触静电载体的同时对衬底进行处理。 在一个实施例中，将导体强制通过介电材料，其被接收在静电载体的导电电极上，以与导电电极物理接触导体，以使基板静电地接合到静电载体上。 在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。 还公开了用于保持用于加工的基材和这种组件的静电载体。

公开(公告)号：US07547850B2

公开(公告)日：2009-06-16

申请号：US11476471

申请日：2006-06-28

申请人： Kyle K. Kirby ,  Warren M. Farnworth

发明人： Kyle K. Kirby ,  Warren M. Farnworth

IPC分类号： H05K1/16

CPC分类号： H01L23/49811 ,  B33Y80/00 ,  G01R1/06727 ,  G01R1/07357 ,  G01R3/00 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/48 ,  H01L24/72 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/351 ,  H05K3/4092 ,  H05K2201/0311 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a silicon wafer or a carrier substrate is provided. At least one layer of a metal or alloy film may be deposited on the substrate or on at least one intervening release layer and patterned to form metal traces. A stressable material, exhibiting an at least partially tensile stress state, may be deposited on the metal traces in a localized region. A portion of the substrate or a portion of the intervening release layer underneath the metal traces may be removed by etching, causing the metal traces to curl upward resulting in the spring contacts. The spring contacts may be used as compliant electrical contacts for electrical devices, such as integrated circuits or carrier substrates. The compliant electrical contacts may also be used for probe cards to test other electrical devices.

摘要翻译： 公开了光刻图案的弹簧触点。 可以使用薄膜处理技术来制造弹簧触点。 提供了诸如硅晶片或载体衬底的衬底。 至少一层金属或合金膜可以沉积在衬底上或至少一个中间释放层上并且被图案化以形成金属迹线。 表现出至少部分拉伸应力状态的可压应材料可以沉积在局部区域的金属迹线上。 可以通过蚀刻去除基底的一部分或金属迹线下方的中间释放层的一部分，导致金属迹线向上卷曲，导致弹簧接触。 弹簧触点可以用作电气装置的柔性电触点，例如集成电路或载体基板。 兼容的电触点也可用于探针卡以测试其他电气设备。

公开(公告)号：US07452743B2

公开(公告)日：2008-11-18

申请号：US11217877

申请日：2005-09-01

申请人： Steven D. Oliver ,  Lu Velicky ,  William Mark Hiatt ,  David R. Hembree ,  Mark E. Tuttle ,  Sidney B. Rigg ,  James M. Wark ,  Warren M. Farnworth ,  Kyle K. Kirby

发明人： Steven D. Oliver ,  Lu Velicky ,  William Mark Hiatt ,  David R. Hembree ,  Mark E. Tuttle ,  Sidney B. Rigg ,  James M. Wark ,  Warren M. Farnworth ,  Kyle K. Kirby

IPC分类号： H01L21/00

CPC分类号： H01L21/00 ,  H01L21/76898 ,  H01L23/552 ,  H01L27/14609 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

摘要： Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.

摘要翻译： 本文公开了用于在晶片级制造多个成像单元的微电子成像单元和方法。 在一个实施例中，制造多个成像单元的方法包括提供具有多个成像管芯的成像工件，所述成像管芯包括集成电路，电耦合到集成电路的外部触点以及可操作地耦合到集成电路的图像传感器。 各个图像传感器包括在图像传感器的周边部分处的至少一个暗电流像素。 该方法包括将覆盖层沉积在工件上并在图像传感器上方。 该方法还包括图案化和选择性地显影覆盖层以在对应的图像传感器上形成分离体积的覆盖层材料。 覆盖层材料的离散体积具有与各个暗电流像素的内侧边缘对准的侧壁，使得暗电流像素不被离散体积覆盖。

公开(公告)号：US07449910B2

公开(公告)日：2008-11-11

申请号：US11348094

申请日：2006-02-06

申请人： Kyle K. Kirby ,  Warren M. Farnworth

发明人： Kyle K. Kirby ,  Warren M. Farnworth

IPC分类号： G01R31/26

CPC分类号： G01R1/06733 ,  B33Y70/00 ,  B33Y80/00 ,  G01R1/06711 ,  G01R1/07314 ,  G01R3/00 ,  H01L23/49811 ,  H01L24/72 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/326 ,  H05K3/4092 ,  H01L2924/00 ,  H01L2224/05599

摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.

摘要翻译： 用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。 每个互连触点包括形成为导电弹簧元件的柔性导电层。 此外，投诉导电层包括用于接合部件触点的尖端和用于弹性地支撑尖端的弹簧部分部分。 一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。 成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。 导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。 互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。