公开(公告)号：US5985708A

公开(公告)日：1999-11-16

申请号：US816596

申请日：1997-03-13

申请人： Akio Nakagawa ,  Naoharu Sugiyama ,  Tomoko Matsudai ,  Norio Yasuhara ,  Atsusi Kurobe ,  Hideyuki Funaki ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

发明人： Akio Nakagawa ,  Naoharu Sugiyama ,  Tomoko Matsudai ,  Norio Yasuhara ,  Atsusi Kurobe ,  Hideyuki Funaki ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

IPC分类号： H01L27/12 ,  H01L29/73 ,  H01L29/739 ,  H01L29/786 ,  H01L21/8249

CPC分类号： H01L29/78696 ,  H01L27/1203 ,  H01L29/7317 ,  H01L29/7394 ,  H01L29/78612 ,  H01L29/78624 ,  H01L29/78639 ,  H01L29/78645 ,  H01L29/78687

摘要： A semiconductor apparatus comprising a vertical type semiconductor device having a first conducting type semiconductor substrate, a drain layer formed on the surface of the semiconductor substrate, a drain electrode formed on the surface of the drain layer, a second conducting type base layer selectively formed on the surface of the semiconductor substrate opposite to the drain layer, a first conducting type source layer selectively formed on the surface of the second conducting type base layer, a source electrode formed on the first conducting type source layer and the second conducting type base layer, and a gate electrode formed in contact with the first conducting type source layer, the second conducting type base layer and the semiconductor substrate through a gate insulating film and a lateral semiconductor device having an insulating layer formed in a region of the surface of the semiconductor substrate different from the second conducting type base layer, and a polycrystalline semiconductor layer formed on the insulating layer and having a first conducting type region and a second conducting type region, wherein the first conducting type source layer of the vertical semiconductor device and the first conducting type region of the polycrystalline semiconductor layer are simultaneously formed.

摘要翻译： 一种半导体装置，包括具有第一导电型半导体衬底的垂直型半导体器件，形成在半导体衬底的表面上的漏极层，形成在漏极层的表面上的漏电极，第二导电型基极层， 所述半导体衬底的与所述漏极层相对的表面，选择性地形成在所述第二导电型基极层的表面上的第一导电型源极层，形成在所述第一导电型源极层和所述第二导电型基极层上的源电极， 以及通过栅极绝缘膜与第一导电型源极层，第二导电型基极层和半导体基板接触形成的栅电极，以及在半导体基板的表面的区域中形成有绝缘层的侧面半导体装置 不同于第二导电型基底层，和多晶 半导体层形成在绝缘层上并具有第一导电类型区域和第二导电类型区域，其中垂直半导体器件的第一导电型源极层和多晶半导体层的第一导电类型区域同时形成。

公开(公告)号：US09105716B2

公开(公告)日：2015-08-11

申请号：US12944632

申请日：2010-11-11

申请人： Miwako Akiyama ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

发明人： Miwako Akiyama ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08 ,  H01L29/417

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

摘要： A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.

摘要翻译： 半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层设置在第一半导体层的主表面上并且具有比第一半导体层的杂质浓度低的第二半导体层; 设置在第二半导体层上的第二导电类型的第三半导体层; 选择性地设置在第三半导体层上的第一导电类型的第四半导体层; 设置在穿过所述第三半导体层并到达所述第二半导体层的沟槽中的栅电极; 与所述第四半导体层接触的第一主电极，并且通过设置成在所述连续的栅电极之间穿过所述第四半导体层的接触槽使所述第三半导体层接触; 设置在与所述第一半导体层的主表面相反的表面上的第二主电极; 以及第二导电类型的第五半导体层，设置在与所述接触槽下方的部分对应的所述第二半导体层的内部。 第五半导体层的最上部与第三半导体层接触，第五半导体层的最下部分的杂质浓度比第五半导体层中的其他部分杂质浓度高，位于第二半导体层中， 第一半导体层，第五半导体层从最上部到最下部较窄。

公开(公告)号：US07910984B2

公开(公告)日：2011-03-22

申请号：US12355591

申请日：2009-01-16

申请人： Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Miwako Akiyama

发明人： Yoshihiro Yamaguchi ,  Yusuke Kawaguchi ,  Miwako Akiyama

IPC分类号： H01L29/76

CPC分类号： H01L27/088 ,  H01L21/823487 ,  H01L23/481 ,  H01L23/482 ,  H01L27/0629 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/7813 ,  H01L29/7825 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate; a lateral MOSFET formed in an upper portion of a first region of the semiconductor substrate; a vertical MOSFET formed in a second region of the semiconductor substrate; a backside electrode formed on a lower surface of the semiconductor substrate and connected to a lower region of source/drain regions of the vertical MOSFET; and a connecting member penetrating the semiconductor substrate and connecting one of source/drain regions of the lateral MOSFET to the backside electrode.

摘要翻译： 半导体器件包括：半导体衬底; 形成在所述半导体衬底的第一区域的上部的横向MOSFET; 形成在所述半导体衬底的第二区域中的垂直MOSFET; 背面电极，其形成在所述半导体衬底的下表面上并且连接到所述垂直MOSFET的源极/漏极区域的下部区域; 以及穿透半导体衬底并将横向MOSFET的源极/漏极区域中的一个连接到背面电极的连接构件。

公开(公告)号：US20080283909A1

公开(公告)日：2008-11-20

申请号：US12122165

申请日：2008-05-16

申请人： Miwako Akiyama ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

发明人： Miwako Akiyama ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734

摘要： A semiconductor device includes a second-conductivity-type base region provided on a first-conductivity-type semiconductor layer, a first-conductivity-type source region provided on the second-conductivity-type base region, a gate insulating film covering an inner wall of a trench which passes through the second-conductivity-type base region and reaching the first-conductivity-type semiconductor layer, a gate electrode buried in the trench via the gate insulating film, and a second-conductivity-type region being adjacent to the second-conductivity-type base region below the first-conductivity-type source region, spaced from the gate insulating film, and having a higher impurity concentration than the second-conductivity-type base region. c≧d is satisfied, where d is a depth from an upper surface of the first-conductivity-type source region to a lower end of the gate electrode, and c is a depth from an upper surface of the first-conductivity-type source region to a lower surface of the second-conductivity-type base region.

摘要翻译： 半导体器件包括设置在第一导电型半导体层上的第二导电型基极区域，设置在第二导电型基极区域上的第一导电型源极区域，覆盖内壁的栅极绝缘膜 通过所述第二导电型基极区域并到达所述第一导电型半导体层的沟槽，经由所述栅极绝缘膜埋设在所述沟槽中的栅电极，以及与所述第二导电型基极区相邻的第二导电型区域 与第一导电型源极区域相邻的第二导电型基极区域，与栅极绝缘膜间隔开，并且具有比第二导电型基极区域更高的杂质浓度。 c> = d，其中d是从第一导电型源极区域的上表面到栅极电极的下端的深度，c是从第一导电型源极区域的上表面开始的深度 源极区域延伸到第二导电型基极区域的下表面。

公开(公告)号：US5777371A

公开(公告)日：1998-07-07

申请号：US716863

申请日：1996-09-20

申请人： Yusuke Kawaguchi ,  Yoshihiro Yamaguchi ,  Hideyuki Funaki

发明人： Yusuke Kawaguchi ,  Yoshihiro Yamaguchi ,  Hideyuki Funaki

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7801 ,  H01L29/7824 ,  H01L29/42368

摘要： A high-breakdown-voltage semiconductor device includes a high-resistance semiconductor layer, a drift layer of the first conductivity type selectively formed in the surface of the high-resistance semiconductor layer, a drain layer formed in the surface of the drift layer of the first conductivity type, base layers of the second conductivity type selectively formed in the surface of the high-resistance semiconductor layer, a plurality of island-shaped source layers of the first conductivity type formed in the surfaces of the base layers of the second conductivity type, a gate electrode formed on the base layers of the second conductivity type between the source layers of the first conductivity type and the drift layer of the first conductivity type and between adjacent source layers of the first conductivity type via a gate insulating film, a drain electrode which contacts the drain layer, and source electrodes which contact both the source layers of the first conductivity type and the base layers of the second conductivity type.

摘要翻译： 高耐压半导体器件包括高电阻半导体层，选择性地形成在高电阻半导体层的表面中的第一导电类型的漂移层，形成在所述高电阻半导体层的漂移层的表面中的漏极层 第一导电类型，选择性地形成在高电阻半导体层的表面中的第二导电类型的基极层，形成在第二导电类型的基极层的表面中的多个第一导电类型的岛状源极层 形成在第一导电类型的源极层和第一导电类型的漂移层之间的第二导电类型的基极层上的栅极电极和经由栅极绝缘膜的第一导电类型的相邻源极层之间， 与漏极层接触的电极以及接触第一导电类型的源极层的源电极 第二导电类型的基层。

公开(公告)号：US08482060B2

公开(公告)日：2013-07-09

申请号：US13052917

申请日：2011-03-21

申请人： Takeshi Uchihara ,  Yusuke Kawaguchi ,  Keiko Kawamura ,  Hitoshi Shinohara ,  Yosefu Fujiki

发明人： Takeshi Uchihara ,  Yusuke Kawaguchi ,  Keiko Kawamura ,  Hitoshi Shinohara ,  Yosefu Fujiki

IPC分类号： H01L29/772

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7808

摘要： According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a gate electrode in a trench shape, a contact region of the second conductivity type, a drain electrode, and a source electrode. The drift region is selectively provided in a drain layer of the first conductivity type from a surface of the drain layer to an inside of the drain layer. The base region is selectively provided in the drift region from a surface of the drift region to an inside of the drift region. The source region is selectively provided in the base region from a surface of the base region to an inside of the base region. The gate electrode penetrates from a part of the source region through the base region adjacent to the part of the source region to reach a part of the drift region in a direction substantially parallel to a major surface of the drain layer. The contact region is selectively provided on the surface of the drift region. The contact region contains an impurity having a concentration higher than an impurity concentration of the base region. The drain electrode is connected to the drain layer. The source electrode is connected to the source region and the contact region. The contact region extends from a side of the drain layer toward the drift region and does not contact the drain layer.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的漂移区域，第二导电类型的基极区域，第一导电类型的源极区域，沟槽形状的栅电极，第二导电类型的接触区域 导电类型，漏电极和源电极。 漂移区选择性地设置在第一导电类型的漏极层中，从漏极层的表面到漏极层的内部。 基极区域选择性地设置在漂移区域中，从漂移区域的表面到漂移区域的内部。 源极区域从基极区域的表面到基极区域的内部选择性地设置在基极区域中。 栅极电极从源极区域的一部分穿过与源极区域相邻的基极区域，以在与漏极层的主表面基本平行的方向上到达漂移区域的一部分。 接触区选择性地设置在漂移区的表面上。 接触区域含有浓度高于碱性区域的杂质浓度的杂质。 漏电极连接到漏极层。 源电极连接到源极区域和接触区域。 接触区域从漏极层的侧面朝向漂移区域延伸，并且不接触漏极层。

公开(公告)号：US07633153B2

公开(公告)日：2009-12-15

申请号：US11778516

申请日：2007-07-16

申请人： Kazuo Shimokawa ,  Takashi Koyanagawa ,  Masako Ooishi ,  Tatsuya Yamada ,  Osamu Usuda ,  Yoshiki Endo ,  Taiki Miura ,  Masaki Toyoshima ,  Ichiro Omura ,  Akio Nakagawa ,  Kenichi Matsushita ,  Yusuke Kawaguchi ,  Haruki Arai ,  Hiroshi Takei ,  Tomohiro Kawano ,  Noriaki Yoshikawa ,  Morio Takahashi ,  Yasuhito Saito ,  Masahiro Urase

发明人： Kazuo Shimokawa ,  Takashi Koyanagawa ,  Masako Ooishi ,  Tatsuya Yamada ,  Osamu Usuda ,  Yoshiki Endo ,  Taiki Miura ,  Masaki Toyoshima ,  Ichiro Omura ,  Akio Nakagawa ,  Kenichi Matsushita ,  Yusuke Kawaguchi ,  Haruki Arai ,  Hiroshi Takei ,  Tomohiro Kawano ,  Noriaki Yoshikawa ,  Morio Takahashi ,  Yasuhito Saito ,  Masahiro Urase

IPC分类号： H01L23/10

CPC分类号： H01L23/3121 ,  H01L21/565 ,  H01L23/36 ,  H01L23/367 ,  H01L23/4822 ,  H01L23/49805 ,  H01L23/49844 ,  H01L24/16 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/84 ,  H01L25/0655 ,  H01L25/165 ,  H01L29/4175 ,  H01L29/7802 ,  H01L29/7806 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40225 ,  H01L2224/73153 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

摘要翻译： 半导体模块包括安装板。 多个电源开关器件芯片通过倒装芯片接合安装在安装板上。 芯片具有上表面和下表面，并且被配置为面向安装板的上表面。 通过倒装芯片接合将驱动IC芯片安装在安装板上。 驱动IC芯片用于驱动形成在多个功率开关器件芯片中的晶体管的栅极。 多个散热构件分别位于多个功率开关器件芯片的下表面上。 提供树脂构件以将单个封装中的多个功率开关器件芯片和驱动IC芯片密封。

公开(公告)号：US20070034894A1

公开(公告)日：2007-02-15

申请号：US11501715

申请日：2006-08-10

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

IPC分类号： H01L29/74

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

公开(公告)号：US07067876B2

公开(公告)日：2006-06-27

申请号：US10139324

申请日：2002-05-07

申请人： Norio Yasuhara ,  Kazutoshi Nakamura ,  Yusuke Kawaguchi

发明人： Norio Yasuhara ,  Kazutoshi Nakamura ,  Yusuke Kawaguchi

IPC分类号： H01L29/76

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4238

摘要： A semiconductor device comprises a semiconductor substrate; a semiconductor layer having a higher resistance than that of said semiconductor substrate and provided on a top surface of said semiconductor substrate; a gate electrode provided on a gate insulating film on the top surface of said semiconductor layer; a drain layer of a first conductivity type selectively provided in a location in said semiconductor layer in one side of said gate electrode; a drain electrode connected to said drain layer; a source layer of the first conductivity type selectively provided in a location in said semiconductor layer in the other side of said gate electrode; an element-side connecting portion selectively provided on said semiconductor layer, which does not reach a channel portion between said source layer and said drain layer of said semiconductor layer and also does not reach to said semiconductor substrate, and which is in contact with said source layer and has lower resistance than that of said semiconductor layer; a contact-side connecting portion selectively provided on said semiconductor layer, having lower resistance than said semiconductor layer and extending deeper toward said semiconductor substrate than said element-side connecting portion; a first source electrode connecting said source layer, said element-side connect portion and said contact-side connect portion; and a bottom electrode provided on the bottom surface of said semiconductor substrate in connection therewith.

公开(公告)号：US20060108590A1

公开(公告)日：2006-05-25

申请号：US11033469

申请日：2005-01-12

申请人： Yusuke Kawaguchi

发明人： Yusuke Kawaguchi

IPC分类号： H01L33/00 ,  H01L31/12 ,  H01L27/15 ,  H01L29/26

CPC分类号： G01N21/6489 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L33/0075

摘要： The group III-V nitride series semiconductor substrate has good-product yield when the band-edge peak light-emission intensity ratio α=N1/N2 is α

摘要翻译： 当带边峰值发光强度比α= N 1 / N 2时，III-V族氮化物系半导体衬底具有良好的产品产量，为α<1 其中N 1是在基板正面的任意光致发光测量位置处的带边峰值发光强度，N 2是带边缘峰值发光强度 对应于光致发光测量位置的衬底背面的峰值发光强度。