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    Semiconductor Devices, Image Sensors, and Methods of Manufacture Thereof
    53.
    发明申请
    Semiconductor Devices, Image Sensors, and Methods of Manufacture Thereof 有权
    半导体器件，图像传感器及其制造方法

    公开(公告)号：US20150214267A1

    公开(公告)日：2015-07-30

    申请号：US14163944

    申请日：2014-01-24

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Sheng-Chau Chen ,  Tung-Ting Wu ,  Cheng-Ta Wu ,  Chih-Hui Huang ,  Yeur-Luen Tu ,  Jhy-Jyi Sze

    IPC分类号： H01L27/146

    CPC分类号： H01L27/14683 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464

    摘要： Semiconductor devices, image sensors, and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a high dielectric constant (k) insulating material disposed over a workpiece, the high k insulating material having a dielectric constant of greater than about 3.9. A barrier layer is disposed over the high k insulating material. A buffer oxide layer including a porous oxide film is disposed between the high k insulating material and the barrier layer. The porous oxide film has a first porosity, and the barrier layer or the high k insulating material has a second porosity. The first porosity is greater than the second porosity.

    摘要翻译： 公开了半导体器件，图像传感器及其制造方法。 在一些实施例中，半导体器件包括设置在工件上方的高介电常数（k）绝缘材料，该高k绝缘材料具有大于约3.9的介电常数。 阻挡层设置在高k绝缘材料上。 包含多孔氧化物膜的缓冲氧化物层设置在高k绝缘材料和阻挡层之间。 多孔氧化膜具有第一孔隙度，并且阻挡层或高k绝缘材料具有第二孔隙率。 第一孔隙度大于第二孔隙率。

    BOND PAD STRUCTURE FOR BONDING IMPROVEMENT
    55.
    发明公开
    BOND PAD STRUCTURE FOR BONDING IMPROVEMENT 审中-公开

    公开(公告)号：US20240355864A1

    公开(公告)日：2024-10-24

    申请号：US18761377

    申请日：2024-07-02

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chin-Wei Liang ,  Sheng-Chau Chen ,  Hsun-Chung Kuang ,  Sheng-Chan Li

    IPC分类号： H01L27/146

    CPC分类号： H01L27/14636 ,  H01L27/1462 ,  H01L27/14685 ,  H01L27/14698

    摘要： A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

    Bond pad structure for bonding improvement
    57.
    发明授权
    Bond pad structure for bonding improvement 有权

    公开(公告)号：US12113090B2

    公开(公告)日：2024-10-08

    申请号：US18365561

    申请日：2023-08-04

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chin-Wei Liang ,  Sheng-Chau Chen ,  Hsun-Chung Kuang ,  Sheng-Chan Li

    IPC分类号： H01L27/146

    CPC分类号： H01L27/14636 ,  H01L27/1462 ,  H01L27/14685 ,  H01L27/14698

    摘要： A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

    IMAGE SENSOR WITH DUAL TRENCH ISOLATION STRUCTURE
    59.
    发明公开
    IMAGE SENSOR WITH DUAL TRENCH ISOLATION STRUCTURE 审中-公开

    公开(公告)号：US20230290672A1

    公开(公告)日：2023-09-14

    申请号：US18320523

    申请日：2023-05-19

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Tzu-Jui Wang ,  Sheng-Chan Li

    IPC分类号： H01L21/762 ,  H01L27/146

    CPC分类号： H01L21/76224 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14643 ,  H01L27/1464

    摘要： In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.