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公开(公告)号：US10079067B1
公开(公告)日：2018-09-18
申请号：US15697469
申请日：2017-09-07
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Shao-Ching Liao , Ping-Kun Wang , Chia-Hua Ho
CPC classification number: G11C16/3422 , G11C7/04 , G11C11/1673 , G11C11/5628 , G11C11/5642 , G11C13/0026 , G11C13/003 , G11C13/004 , G11C16/0483 , G11C16/24 , G11C16/28 , G11C2013/0057
Abstract: A data read method and a non-volatile memory apparatus using the same are provided. The data read method includes: obtaining a first read current and a second read current from a memory cell pair of the non-volatile memory; performing a calculation operation according to the first read current and the second read current to obtain a calculation result; and determining a logical state of the memory cell pair according to the calculation result. The calculation operation includes at least a signal addition operation and a signal multiplying operation.
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公开(公告)号：US20180233665A1
公开(公告)日：2018-08-16
申请号：US15949078
申请日：2018-04-10
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Po-Yen Hsu , Yi-Hsiu Chen , Ting-Ying Shen , Bo-Lun Wu , Meng-Hung Lin , Chia-Hua Ho , Ming-Che Lin
CPC classification number: H01L45/146 , H01L27/2463 , H01L45/08 , H01L45/122 , H01L45/1253 , H01L45/1266 , H01L45/1616
Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.
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公开(公告)号：US09972779B2
公开(公告)日：2018-05-15
申请号：US14967386
申请日：2015-12-14
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Po-Yen Hsu , Yi-Hsiu Chen , Ting-Ying Shen , Bo-Lun Wu , Meng-Hung Lin
CPC classification number: H01L45/1266 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/124 , H01L45/146
Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.
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Patent Agency Ranking
公开(公告)号：US09859338B2
公开(公告)日：2018-01-02
申请号：US15075215
申请日：2016-03-21
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Chia-Hua Ho
CPC classification number: H01L27/249 , H01L27/2436 , H01L27/2454 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/1616
Abstract: Provided is a three-dimensional resistive memory including a channel pillar, a first gate pillar, a first gate dielectric layer, first and second stacked structures, a variable resistance pillar and an electrode pillar. The channel pillar is on a substrate. The first gate pillar is on the substrate and at a first side of the channel pillar. The first gate dielectric layer is between the channel pillar and the first gate pillar. The first and second stacked structures are on the substrate and respectively at opposite second and third sides of the channel pillar. Each of the first and second stacked structures includes conductive material layers and insulating material layers alternately stacked. The variable resistance pillar is on the substrate and at a side of the first stacked structure opposite to the channel pillar. The electrode pillar is on the substrate and inside of the variable resistance pillar.
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公开(公告)号：US09824733B2
公开(公告)日：2017-11-21
申请号：US14918574
申请日：2015-10-21
Applicant: Winbond Electronics Corp.
Inventor： Shao-Ching Liao , Ping-Kun Wang , Frederick Chen
CPC classification number: G11C11/00 , G11C5/147 , G11C11/5642 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , H01L27/2409 , H01L45/00
Abstract: An operating method for a resistive memory cell and a resistive memory are provided. The operating method for the resistive memory cell includes following steps. A forming operation for the resistive memory cell is performed. Whether the resistive memory cell is in a first state is determined, wherein the first state is corresponding to a first operation. When the resistive memory cell is not in the first state, a complementary switching operation regarding a second operation for the resistive memory cell is performed, so that the resistive memory cell generates a complementary switching phenomenon regarding the second operation. Thus, the resistive memory cell which cannot retain data by normal forming operation can effectively obtain the data retention capability by the complementary switching phenomenon.
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公开(公告)号：US09716223B1
公开(公告)日：2017-07-25
申请号：US15204215
申请日：2016-07-07
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen
CPC classification number: H01L45/146 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1675
Abstract: A resistive random access memory device includes a bottom electrode, a plurality of memory stacks separately formed over the bottom electrode, a third oxygen diffusion barrier layer formed between the memory stacks, and a top electrode formed over the plurality of memory stacks and the third oxygen diffusion barrier layer. Each of the plurality of memory stacks includes a resistive switching layer formed over the bottom electrode, a first oxygen diffusion barrier layer formed over the resistive switching layer, a conductive oxygen reservoir layer formed over the first oxygen diffusion barrier layer, and a second oxygen diffusion barrier layer formed over the conductive oxygen reservoir layer.
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公开(公告)号：US09412445B1
公开(公告)日：2016-08-09
申请号：US14824081
申请日：2015-08-12
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Meng-Hung Lin , Ping-Kun Wang
CPC classification number: G11C13/004 , G11C7/04 , G11C13/0002 , G11C13/0004 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C29/04 , G11C29/50 , G11C2013/0057
Abstract: A resistive memory apparatus and a reading method thereof are provided. In this method, two reading pulses are applied to a resistive memory cell, such that a first reading resistance and a second reading resistance of the resistive memory cell at different temperatures are sequentially obtained. Next, a resistive state of the second reading resistance is determined according to the reading resistances and the temperatures corresponding to the reading resistances. Thereafter, a logic level of storage data of the resistive memory cell is determined according to the resistive state of the second reading resistance.
Abstract translation: 提供了一种电阻式存储装置及其读取方法。 在该方法中，将两个读取脉冲施加到电阻性存储单元，使得在不同温度下顺次获得电阻式存储单元的第一读取电阻和第二读取电阻。 接下来，根据读取电阻和对应于读取电阻的温度来确定第二读取电阻的电阻状态。 此后，根据第二读取电阻的电阻状态来确定电阻性存储单元的存储数据的逻辑电平。
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公开(公告)号：US09373391B1
公开(公告)日：2016-06-21
申请号：US14850974
申请日：2015-09-11
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Wen-Hsiung Chang , Chien-Min Wu
CPC classification number: G11C13/0002 , G11C5/06 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/0033 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463
Abstract: A resistive memory apparatus is provided. The resistive memory apparatus includes a plurality of memory cell pairs, and each of the memory cell pairs includes an active area, first and second word lines, a source line, first and second resistors and first and second bit lines. The active area is formed on a substrate, and the first and second word lines are formed on the substrate, and intersected with the active area. The source line is formed on the substrate and coupled to the active area. The first and second resistors are disposed on the substrate, and respectively coupled to the active area. The first and second bit lines are formed on the first and second resistors and coupled to the first and second resistors. The first and second bit lines are extended along a first direction which is substantially parallel to the first and second word lines.
Abstract translation: 提供了一种电阻式存储装置。 电阻式存储装置包括多个存储单元对，并且每个存储单元对包括有源区，第一和第二字线，源极线，第一和第二电阻以及第一和第二位线。 有源区形成在基板上，第一和第二字线形成在基板上，并与有源区相交。 源极线形成在衬底上并耦合到有源区。 第一和第二电阻器设置在基板上，并且分别耦合到有源区域。 第一和第二位线形成在第一和第二电阻上并耦合到第一和第二电阻器。 第一和第二位线沿着基本上平行于第一和第二字线的第一方向延伸。
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