公开(公告)号：US08975678B2

公开(公告)日：2015-03-10

申请号：US13867213

申请日：2013-04-22

申请人： Renesas Electronics Corporation

发明人： Yoshiyuki Kawashima ,  Koichi Toba ,  Yasushi Ishii ,  Toshikazu Matsui ,  Takashi Hashimoto

IPC分类号： H01L49/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

摘要： In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

摘要翻译： 关于包括电容器元件的半导体器件，提供了一种能够提高电容器元件的可靠性的技术。 电容器元件形成在半导体衬底上形成的元件隔离区域中。 电容器元件包括通过电容器绝缘膜形成在下电极上的下电极和上电极。 基本上，下电极和上电极由形成在多晶硅膜的表面上的多晶硅膜和硅化钴膜形成。 形成在上电极上的钴硅化物膜的端部与上电极的端部间隔开一定距离。 此外，形成在下电极上的钴硅化物膜的端部与上电极和下电极之间的边界间隔一定距离。

公开(公告)号：US20150063024A1

公开(公告)日：2015-03-05

申请号：US14013370

申请日：2013-08-29

申请人： Micron Technology, Inc.

发明人： Aaron S. YIP ,  Mark A. HELM ,  Ramin GHODSI

IPC分类号： G11C16/02

CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

摘要： In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

公开(公告)号：US20150048506A1

公开(公告)日：2015-02-19

申请号：US13965269

申请日：2013-08-13

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Yi-Hsuan Hsiao ,  Yen-Hao Shih ,  Shih-Hung Chen ,  Hang-Ting Lue

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L27/12

CPC分类号： H01L27/0688 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

摘要： A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.

摘要翻译： 提供了一种存储器件及其制造方法。 存储器件包括衬底，3D存储器阵列，外围电路和导电连接结构。 3D存储器阵列和外围电路堆叠在基板上。 外围电路包括图案化金属层和电连接到图案化金属层的接触结构。 导电连接结构电连接到图案化的金属层。 3D存储器阵列经由导电连接结构电连接到外围电路。

公开(公告)号：US08951869B2

公开(公告)日：2015-02-10

申请号：US14139991

申请日：2013-12-24

申请人： Renesas Electronics Corporation

发明人： Keisuke Tsukamoto ,  Tatsuyoshi Mihara

IPC分类号： H01L21/8234 ,  H01L21/8239 ,  H01L21/28 ,  H01L21/285 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/51

CPC分类号： H01L27/11531 ,  H01L21/265 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/324 ,  H01L27/11521 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S438/926

摘要： A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

摘要翻译： 在半导体衬底的存储单元区域中形成非易失性存储器的存储单元的控制栅极电极和存储栅电极，并且在外围电路区域中形成虚拟栅电极。 然后，在存储单元区域中形成用于存储单元的源极或漏极的n +型半导体区域，并且在外围电路区域中形成用于MISFET的源极或漏极的n +型半导体区域。 然后，在n +型半导体区域上形成金属硅化物层，但是在控制栅电极，存储栅电极和栅电极之上不形成金属硅化物层。 随后，去除栅电极并用MISFET的栅电极代替。 然后，在去除栅电极并用MISFET的栅电极代替之后，在存储栅电极和控制栅极上形成金属硅化物层。

公开(公告)号：US08937340B2

公开(公告)日：2015-01-20

申请号：US13899629

申请日：2013-05-22

申请人： Macronix International Co., Ltd.

发明人： Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L23/52 ,  H01L29/66 ,  G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792

摘要： Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

摘要翻译： 存储单元包括薄膜晶体管，堆叠阵列，采用无接合的NAND配置的带隙工程隧道层。 单元包括在绝缘层上形成的半导体条中的沟道区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括多层结构，所述多层结构包括至少一层，所述层具有低于与所述沟道区的界面处的空穴 - 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且设置在绝缘层上方的栅电极描述了阵列和操作方法。

公开(公告)号：US20140339613A1

公开(公告)日：2014-11-20

申请号：US14015184

申请日：2013-08-30

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kenichi IDE

IPC分类号： H01L29/49 ,  H01L21/28

CPC分类号： H01L29/4941 ,  H01L21/28052 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/11524 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate, and a gate insulator arranged on the semiconductor substrate. The device further includes a gate electrode including a semiconductor layer and a metal layer which are sequentially arranged on the gate insulator. The device further includes a contact plug arranged on the gate electrode to penetrate the metal layer, and having a bottom surface at a level lower than an upper surface of the semiconductor layer.

摘要翻译： 在一个实施例中，半导体器件包括半导体衬底和布置在半导体衬底上的栅极绝缘体。 该器件还包括依次布置在栅极绝缘体上的包括半导体层和金属层的栅电极。 该装置还包括布置在栅电极上以穿透金属层的接触插塞，并且具有比半导体层的上表面低的水平面的底表面。

公开(公告)号：US08877647B2

公开(公告)日：2014-11-04

申请号：US13858094

申请日：2013-04-08

申请人： Winbond Electronics Corp.

发明人： Jen-Hsiang Tsai

IPC分类号： H01L21/306

CPC分类号： H01L21/306 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11573

摘要： A method of forming memory device is provided. A substrate having at least two cell areas and at least one peripheral area between the cell areas is provided. A target layer, a sacrificed layer and a first mask layer having first mask patterns in the cell areas and second mask patterns in the peripheral area are sequentially formed on the substrate. Sacrificed layer is partially removed to form sacrificed patterns by using the first mask layer as a mask. Spacers are formed on sidewalls of the sacrificed patterns. The sacrificed patterns and at least the spacers in the peripheral area are removed. A second mask layer is formed in the cell areas. Target layer is partially removed, using the second mask layer and remaining spacers as a mask, to form word lines in the cell areas and select gates in a portion of cell areas adjacent to the peripheral area.

摘要翻译： 提供了一种形成存储器件的方法。 提供了具有至少两个单元区域和单元区域之间的至少一个外围区域的基板。 在基板上顺序地形成目标层，牺牲层和在单元区域中具有第一掩模图案的第一掩模层和外围区域中的第二掩模图案。 通过使用第一掩模层作为掩模，部分去除牺牲层以形成牺牲图案。 间隔物形成在牺牲图案的侧壁上。 去除牺牲图案和至少周边区域中的间隔物。 在细胞区域中形成第二掩模层。 使用第二掩模层和剩余的间隔物作为掩模来部分去除目标层，以在单元区域中形成字线，并在邻近周边区域的单元区域的一部分中选择栅极。

公开(公告)号：US20140312404A1

公开(公告)日：2014-10-23

申请号：US13865267

申请日：2013-04-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Anthony I. Chou ,  Arvind Kumar

IPC分类号： H01L27/12 ,  H01L27/105

CPC分类号： H01L27/1203 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/1207 ,  H01L29/7883

摘要： A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region.

摘要翻译： 提供用于集成SOI CMOS FET和NVRAM存储器件的结构和方法。 该结构包括含有半导体衬底，SOI层和形成在半导体衬底和SOI层之间的BOX层的SOI衬底。 SOI衬底包括预定义的SOI器件和NVRAM器件区域。 在SOI器件区域中形成SOI FET。 SOI FET包括BOX层和SOI层的部分，SOI FET栅极电介质层和栅极导体层。 该结构还包括形成在NVRAM器件区域中的NVRAM器件。 NVRAM器件包括隧道氧化物，浮动栅极，阻塞氧化物和控制栅极层。 隧道氧化物层与SOI器件区域中BOX层的部分共面。 浮置栅极层与SOI器件区域中的半导体层的部分共面。

公开(公告)号：US20140256099A1

公开(公告)日：2014-09-11

申请号：US13794024

申请日：2013-03-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hung-Cheng SUNG ,  Yue-Der CHIH ,  Chia-Hsing CHEN

IPC分类号： G06F17/50 ,  H01L29/66

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/06 ,  G06F2217/78 ,  H01L27/0207 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.

摘要翻译： 一种设计电荷俘获存储器阵列的方法，包括设计浮栅存储器阵列布局。 浮动栅极存储器布局包括第一类型的晶体管，浮动栅极存储器阵列布局的存储器单元之间的电连接，第一输入/输出（I / O）接口，第一类型的电荷泵和I / O块 。 该方法还包括使用处理器来修改浮动栅极存储器阵列布局，以用与第一类型的晶体管不同的第二类型的晶体管代替第一类型的晶体管。 该方法还包括确定I / O块和第二类型的晶体管之间的工作电压差。 该方法还包括使用处理器修改浮动栅极存储器阵列布局，以基于所确定的工作电压差来修改第一电荷泵。

公开(公告)号：US08786009B2

公开(公告)日：2014-07-22

申请号：US12902247

申请日：2010-10-12

申请人： Kang-Uk Kim ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

发明人： Kang-Uk Kim ,  Yong-Chul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

IPC分类号： H01L29/78

CPC分类号： H01L21/02002 ,  H01L21/185 ,  H01L21/743 ,  H01L23/53242 ,  H01L23/53257 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate structure including a first substrate and a second substrate, and a buried wiring interposed between the first substrate and the second structure, where the buried wiring is in direct contact with the second substrate. The semiconductor device further includes a vertical transistor located in the second substrate of the substrate structure. The vertical transistor includes a gate electrode and a semiconductor pillar, and the buried wiring is one of source electrode or a drain electrode of the vertical transistor.

摘要翻译： 半导体器件包括包括第一衬底和第二衬底的衬底结构，以及插入在第一衬底和第二结构之间的掩埋布线，其中掩埋布线与第二衬底直接接触。 半导体器件还包括位于衬底结构的第二衬底中的垂直晶体管。 垂直晶体管包括栅极和半导体柱，并且埋入布线是垂直晶体管的源电极或漏极之一。