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    PCB WITH RF SIGNAL PATHS
    51.
    发明申请
    PCB WITH RF SIGNAL PATHS 审中-公开
    带射频信号线的PCB

    公开(公告)号：US20150171500A1

    公开(公告)日：2015-06-18

    申请号：US14572785

    申请日：2014-12-17

    Applicant: ADVANCED DIGITAL BROADCAST S.A.

    Inventor： Piotr GRZELKA ,  Robert GIZYCKI

    IPC: H01P5/00

    CPC classification number: H01P5/00 ,  H05K1/0218 ,  H05K1/0225 ,  H05K1/0243 ,  H05K2201/0723 ,  H05K2201/09327 ,  H05K2201/10189

    Abstract: A printed circuit board (PCB) with radio frequency (RF) signal paths, comprising a first RF signal connector (141) connected to a first signal path (111) and a second RF connector (142) connected to a second signal path (121), wherein the PCB comprises at least three layers (110, 120, 130) and wherein the first signal path (111) is routed on the first layer (110), the second signal path (121) is routed on the second layer (120), and a third layer (130) between the first layer (110) and the second layer (130) has a ground plane (131) in an area (132) extending at least between the first signal path (111) and the second signal path (121).

    Abstract translation: 一种具有射频（RF）信号路径的印刷电路板（PCB），包括连接到第一信号路径（111）的第一RF信号连接器（141）和连接到第二信号路径（121）的第二RF连接器（142） ），其中所述PCB包括至少三层（110,120,130），并且其中所述第一信号路径（111）在所述第一层（110）上布线，所述第二信号路径（121）在所述第二层 120），并且在第一层（110）和第二层（130）之间的第三层（130）在至少在第一信号路径（111）和第二层（130）之间延伸的区域（132）中具有接地平面（131） 第二信号路径（121）。

    Printed circuit board
    52.
    发明授权
    Printed circuit board 有权
    印刷电路板

    公开(公告)号：US08748753B2

    公开(公告)日：2014-06-10

    申请号：US13410311

    申请日：2012-03-02

    Applicant: Fuk Ming Lam

    Inventor： Fuk Ming Lam

    IPC: H05K1/16

    CPC classification number: H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K2201/09327

    Abstract: A printed circuit board includes a first conductive layer that includes a first transmission line portion and two soldering pads, a first insulating layer disposed under the first conductive layer, a fourth conductive layer disposed under the first insulating layer and including a second transmission line portion, two through-hole vias respectively disposed across the first insulating layer, and two capacitors respectively connecting the first transmission line portion and the two soldering pads. The two through-hole vias are directly connected with the two soldering pads and extending the connection to the second transmission line portion respectively.

    Abstract translation: 印刷电路板包括第一导电层，其包括第一传输线部分和两个焊盘，设置在第一导电层下的第一绝缘层，设置在第一绝缘层下方并包括第二传输线部分的第四导电层， 分别设置在第一绝缘层两侧的两个通孔通孔和分别连接第一传输线部分和两个焊盘的两个电容器。 两个通孔通孔与两个焊盘直接连接，并将连接分别延伸到第二传输线部分。

    PRINTED CIRCUIT BOARD
    53.
    发明申请
    PRINTED CIRCUIT BOARD 审中-公开
    印刷电路板

    公开(公告)号：US20140153200A1

    公开(公告)日：2014-06-05

    申请号：US14086982

    申请日：2013-11-22

    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.

    Inventor： SHAO-YOU TANG

    IPC: H05K1/02

    CPC classification number: H05K1/0236 ,  H01P1/2005 ,  H05K1/05 ,  H05K1/165 ,  H05K2201/09327

    Abstract: A printed circuit board includes a ground layer, a metal board, a via, and a power layer. The metal board is arranged between the ground layer and the power layer. The via is electrically connected between the metal board and the power layer. The power layer is made of a number of wires.

    Abstract translation: 印刷电路板包括接地层，金属板，通孔和电源层。 金属板布置在接地层和电源层之间。 通孔电连接在金属板和电源层之间。 功率层由多根导线组成。

    Reduction of jitter in a semiconductor device by controlling printed circuit board and package substrate stackup
    55.
    发明授权
    Reduction of jitter in a semiconductor device by controlling printed circuit board and package substrate stackup 有权
    通过控制印刷电路板和封装衬底叠层来减少半导体器件中的抖动

    公开(公告)号：US07692101B2

    公开(公告)日：2010-04-06

    申请号：US12008353

    申请日：2008-01-09

    Applicant: Anthony T. Duong

    Inventor： Anthony T. Duong

    IPC: H05K1/00

    CPC classification number: H05K1/0216 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K1/0262 ,  H05K1/0298 ,  H05K2201/09327 ,  H05K2201/10212 ,  H05K2201/10734

    Abstract: A model and method are provided for lowering device jitter by controlling the stackup of PCB planes so as to minimize inductance between a FPGA and PCB voltage planes for critical core voltages within the FPGA. Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die.

    Abstract translation: 提供了一种通过控制PCB平面堆叠来降低器件抖动的模型和方法，以便最小化FPGA和PCB电压平面之间对FPGA内部关键内核电压的电感。 此外，提供了一种模型和方法，用于通过控制封装衬底平面的堆叠来降低抖动，以便最小化晶片和衬底电压平面之间对芯片内的关键核心电压的电感。

    Reduction of jitter in a semiconductor device by controlling printed ciucuit board and package substrate stackup
    57.
    发明申请
    Reduction of jitter in a semiconductor device by controlling printed ciucuit board and package substrate stackup 有权
    通过控制印刷电路板和封装衬底叠层来减少半导体器件中的抖动

    公开(公告)号：US20090173520A1

    公开(公告)日：2009-07-09

    申请号：US12008353

    申请日：2008-01-09

    Applicant: Anthony T. Duong

    Inventor： Anthony T. Duong

    IPC: H05K1/00

    CPC classification number: H05K1/0216 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K1/0262 ,  H05K1/0298 ,  H05K2201/09327 ,  H05K2201/10212 ,  H05K2201/10734

    Abstract: A model and method are provided for lowering device jitter by controlling the stackup of PCB planes so as to minimize inductance between a FPGA and PCB voltage planes for critical core voltages within the FPGA. Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die.

    Abstract translation: 提供了一种通过控制PCB平面堆叠来降低器件抖动的模型和方法，以便最小化FPGA和PCB电压平面之间对FPGA内部关键内核电压的电感。 此外，提供了一种模型和方法，用于通过控制封装衬底平面的堆叠来降低抖动，以便最小化晶片和衬底电压平面之间对芯片内的关键核心电压的电感。

    Electrical connector defining a power plane
    58.
    发明授权
    Electrical connector defining a power plane 有权
    电连接器定义电源平面

    公开(公告)号：US07544070B2

    公开(公告)日：2009-06-09

    申请号：US10884330

    申请日：2004-07-02

    Applicant: David Louis Spengler

    Inventor： David Louis Spengler

    IPC: H01R13/648

    CPC classification number: G06F1/189 ,  G06F1/187 ,  H01R13/6471 ,  H05K1/0216 ,  H05K2201/09327

    Abstract: An electronics cabinet is provided comprising an electrical connector in electrical communication with a printed circuit board (PCB) comprising a PCB power plane, the connector comprising a plurality of power contacts defining a connector power plane adapted for receiving a substantially even power load distribution from the PCB power plane among the power contacts.

    Abstract translation: 提供一种电子柜，其包括与包括PCB电源平面的印刷电路板（PCB）电连通的电连接器，所述连接器包括多个电源触点，所述电源触点限定连接器电源平面，所述连接器电源平面适于从 PCB电源平面之间的电源触点。

    MULTILAYER PWB AND A METHOD FOR PRODUCING THE MULTILAYER PWB
    59.
    发明申请
    MULTILAYER PWB AND A METHOD FOR PRODUCING THE MULTILAYER PWB 审中-公开
    多层印刷电路板和多层印刷电路板的制造方法

    公开(公告)号：US20090008139A1

    公开(公告)日：2009-01-08

    申请号：US11772904

    申请日：2007-07-03

    Applicant: Patrik Lundell ,  Stefan Eskilsson ,  Thomas Ahlberg

    Inventor： Patrik Lundell ,  Stefan Eskilsson ,  Thomas Ahlberg

    IPC: H05K1/18 ,  H05K1/00 ,  H05K3/00

    CPC classification number: H05K1/0253 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09627 ,  Y10T29/49155

    Abstract: A multilayered printed wiring board, a multilayer PWB, and a method for manufacturing the same. The multilayer PWB comprises a first main surface and an opposing second main surface, where the multilayer PWB has a height being defined by the distance from the first main surface to the opposing second main surface. The two surfaces and the height together define the thickness of the multilayer PWB. The multilayer PWB comprises a reference ground plane, a microstrip conductor separated from the reference ground plane by a first dielectric layer and a stripline conductor connected with the microstrip conductor and being separated from the reference ground plane by a second dielectric layer. The reference ground plane is formed by two or more different partial reference ground planes positioned at different layers of the multilayer PWB. Furthermore, the reference ground plane is moveable from the first partial reference ground plane to the second partial reference ground plane when a signal current transits from the microstrip conductor to the stripline conductor, and vice versa.

    Abstract translation: 多层印刷布线板，多层印刷电路板及其制造方法。 多层PWB包括第一主表面和相对的第二主表面，其中多层PWB具有由第一主表面到相对的第二主表面的距离限定的高度。 两个表面和高度一起限定了多层PWB的厚度。 多层PWB包括参考接地平面，通过第一电介质层与参考接地层分离的微带线导体和与微带导体连接的带状线导体，并通过第二电介质层与基准接地平面分离。 参考接地层由位于多层PWB的不同层的两个或多个不同的部分参考接地层形成。 此外，当信号电流从微带导体转移到带状线导体时，参考接地层可以从第一部分参考接地层移动到第二部分参考接地层，反之亦然。

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