Nonvolatile memory data recovery after power failure
    53.
    发明授权
    Nonvolatile memory data recovery after power failure 有权
    停电后非易失性存储器数据恢复

    公开(公告)号:US09478271B2

    公开(公告)日:2016-10-25

    申请号:US13854263

    申请日:2013-04-01

    摘要: A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more of the pages subsequent to the unsafe zone. Step (D) may resume operation of the solid-state drive by writing new data subsequent to the pad zone.

    摘要翻译: 公开了断电后的数据恢复方法。 该方法可以包括步骤(A)至(D)。 步骤(A)可以确定固态驱动器的最后断电是不安全的掉电。 响应于确定固态驱动器的最后断电是不安全的电源,步骤(B)可以搜索固态驱动器的非易失性存储器的多个页面中的至少一些以定义不安全区域 -下。 步骤(C)可以限定包括不安全区域之后的一个或多个页面的垫区域。 步骤(D)可以通过在焊盘区域之后写入新的数据来恢复固态驱动器的操作。

    Data storage device, controller, and operating method of data storage device
    54.
    发明授权
    Data storage device, controller, and operating method of data storage device 有权
    数据存储设备,数据存储设备的控制器和操作方法

    公开(公告)号:US09153332B2

    公开(公告)日:2015-10-06

    申请号:US14059852

    申请日:2013-10-22

    摘要: A nonvolatile memory is provided which includes a memory cell array including a plurality of nonvolatile memory cells; a decoder connected with the memory cell array through a plurality of word lines; a data input/output circuit connected with the memory cell array through a plurality of bit lines; a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal; and control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.

    摘要翻译: 提供一种非易失性存储器,其包括:包括多个非易失性存储单元的存储单元阵列; 通过多个字线与存储单元阵列连接的解码器; 通过多个位线与存储单元阵列连接的数据输入/输出电路; 电压检测器,被配置为检测电源电压的变化以输出电压变化信号; 以及控制逻辑,被配置为控制解码器和数据输入/输出电路,使得存储在存储单元阵列处的数据响应于电压变化信号而无效。

    Method for securely storing data in a memory of a portable data carrier
    55.
    发明授权
    Method for securely storing data in a memory of a portable data carrier 有权
    用于将数据安全地存储在便携式数据载体的存储器中的方法

    公开(公告)号:US08838925B2

    公开(公告)日:2014-09-16

    申请号:US13129417

    申请日:2009-08-20

    申请人: Wolfgang Rankl

    发明人: Wolfgang Rankl

    CPC分类号: G06F21/79

    摘要: A method for securely storing data in a multilevel memory of a portable data carrier. The multilevel memory includes one or several multilevel memory cells (SZ) which can assume respectively at least three levels (E, NE). The at least three levels represent a different data content, regarding which respective levels (E, NE) of a memory cell (SZ) are defined as valid or invalid. The levels (E, NE) of a respective memory cell (SZ) are selectively defined as valid or invalid in dependence on a required security level.

    摘要翻译: 一种用于将数据安全地存储在便携式数据载体的多级存储器中的方法。 多级存储器包括一个或多个多级存储器单元(SZ),其可分别承担至少三个级别(E,NE)。 至少三个级别表示不同的数据内容,关于存储器单元(SZ)的各个级别(E,NE)被定义为有效或无效。 相应存储单元(SZ)的电平(E,NE)根据所需的安全级别有选择地定义为有效或无效。

    Memory card that supports file system interoperability
    56.
    发明申请
    Memory card that supports file system interoperability 有权
    支持文件系统互操作性的存储卡

    公开(公告)号:US20050154819A1

    公开(公告)日:2005-07-14

    申请号:US10754483

    申请日:2004-01-09

    摘要: A removable data storage device that intelligently operates as one large data storage region or as multiple, smaller data storage regions is disclosed. The removable data storage device can be used in not only modern electronic products (using 32-bit addressing) but also legacy products (using 16-bit addressing). A host device can couple to the removable storage device to access data stored in/to the removable storage device. As an example, the removable data storage device can be a memory card.

    摘要翻译: 公开了一种可移动数据存储设备,其智能地操作为一个大数据存储区域或多个较小的数据存储区域。 可移动数据存储设备不仅可以用于现代电子产品(使用32位寻址),还可以用于传统产品(使用16位寻址)。 主机设备可以耦合到可移动存储设备以访问存储在/移动存储设备中的数据。 作为示例,可移动数据存储设备可以是存储卡。

    Fuse circuit
    57.
    发明申请
    Fuse circuit 失效
    保险丝电路

    公开(公告)号:US20050041507A1

    公开(公告)日:2005-02-24

    申请号:US10692951

    申请日:2003-10-27

    申请人: Nobuaki Otsuka

    发明人: Nobuaki Otsuka

    CPC分类号: G11C17/18 G11C17/16

    摘要: One fuse set is constituted of a plurality of fuse blocks. Each of the blocks includes a sub-fuse set constituted of fuse elements electrically programmable, and a program control circuit which controls programming of the fuse elements. One of the fuse elements is an enable bit representing validity/invalidity of the sub-fuse set. One fuse block becoming an object of the programming is determined in accordance with a value of the enable bit.

    摘要翻译: 一个熔丝组由多个熔丝块组成。 每个块包括由可电气可编程的熔丝元件构成的子熔丝组,以及控制熔丝元件的编程的程序控制电路。 熔丝元件之一是表示子熔丝组的有效/无效的使能位。 根据使能位的值确定成为编程对象的一个​​熔丝块。

    EPROM encryption code decoding prevention circuit for semiconductor
memory device
    60.
    发明授权
    EPROM encryption code decoding prevention circuit for semiconductor memory device 失效
    用于半导体存储器件的EPROM加密码解码防止电路

    公开(公告)号:US6028931A

    公开(公告)日:2000-02-22

    申请号:US896679

    申请日:1997-07-18

    申请人: Sung Sik Kim

    发明人: Sung Sik Kim

    CPC分类号: G11C16/22 G11C8/20

    摘要: An encryption code decoding prevention circuit for a semiconductor memory device, such as an EPROM, includes a plurality of encryption code cells, an encryption word line operator, a word line operator, a plurality of read data encrypting processors for encrypting data output from memory cells, and an output data detector for enabling an output detecting signal when all bit lines are judged not to have data thereon, by checking an n-bit output applied from the read data encrypting processors to an output buffer. The output buffer amplifies the n-bit data output from the read data encrypting processors and outputs an output data of "1" each time a carry value is applied thereto from the encryption word line operator. The circuit prevents encrypted data from being exposed by making it appear as if unused memory cells are in use by simulating data values of "1" for each of the unused cells.

    摘要翻译: 用于诸如EPROM的半导体存储器件的加密码解码防止电路包括多个加密代码单元,加密字线操作符,字线操作器,用于加密从存储器单元输出的数据的多个读取数据加密处理器 以及输出数据检测器,通过将从读取的数据加密处理器施加的n位输出检查到输出缓冲器,当所有位线被判断为不具有数据时,使能输出检测信号。 输出缓冲器放大从读取的数据加密处理器输出的n位数据,并且每当从加密字线操作符向其施加进位值时,输出“1”的输出数据。 该电路通过使每个未使用的单元模拟数据值“1”看起来像未使用的存储器单元一样被暴露。