公开(公告)号：US20170363507A1

公开(公告)日：2017-12-21

申请号：US15694156

申请日：2017-09-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS SA

Inventor： Jean-Francois Carpentier ,  Patrick Le Maitre ,  Jean-Robert Manouvrier ,  Charles Baudot ,  Bertrand Borot

IPC: G01M11/02 ,  G02B6/12 ,  G02B6/28 ,  G02B6/34

CPC classification number: G01M11/02 ,  G01M11/33 ,  G01R31/2656 ,  G01R31/27 ,  G01R31/2884 ,  G01R31/303 ,  G01R31/311 ,  G01R31/31728 ,  G01R35/00 ,  G02B6/00 ,  G02B6/12004 ,  G02B6/2808 ,  G02B6/34

Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.

公开(公告)号：US09810823B2

公开(公告)日：2017-11-07

申请号：US15357871

申请日：2016-11-21

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Romain Girard Desprolet ,  Sandrine Lhostis ,  Salim Boutami

IPC: H01Q15/02 ,  G02B5/20 ,  H01L27/146

CPC classification number: G02B5/208 ,  G02B5/20 ,  G02B5/204 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14645 ,  H01L27/14649

Abstract: An infrared high-pass plasmonic filter includes a copper layer interposed between two layers of a dielectric material. An array of patterned openings extend through the copper layer and are filled with the dielectric material. Each patterned opening is in the shape of a greek cross, with the arms of adjacent patterns being collinear. A ratio of the width to the length of each arm is in the range from 0.3 to 0.6, and the distance separating the opposite ends of arms of adjacent patterns is shorter than 10 nm.

公开(公告)号：US20170304867A1

公开(公告)日：2017-10-26

申请号：US15515856

申请日：2015-09-30

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS ,  UNIVERSITE GRENOBLE ALPES

Inventor： Fabrice CASSET ,  Skandar BASROUR ,  Cédrick CHAPPAZ ,  Jean-Sébastien DANEL

IPC: B06B3/00 ,  H01L41/18 ,  B06B1/06 ,  H01L41/25 ,  B06B1/04

CPC classification number: B06B3/00 ,  B06B1/045 ,  B06B1/06 ,  B81B3/0021 ,  B81B3/0024 ,  B81B2201/032 ,  H01L41/094 ,  H01L41/18 ,  H01L41/25

Abstract: A mechanical structure comprising a stack including an active substrate and at least one actuator designed to generate vibrations at the active substrate, the stack comprises an elementary structure for amplifying the vibrations: positioned between the actuator and the active substrate, the structure designed to transmit and amplify the vibrations; and comprising at least one trench, located between the actuator and the active substrate. A method for manufacturing the structure comprising the use of a temporary substrate is provided.

公开(公告)号：US09793396B2

公开(公告)日：2017-10-17

申请号：US15169495

申请日：2016-05-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing Liu ,  Thomas Skotnicki

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/28 ,  H01L29/08 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

公开(公告)号：US09793312B1

公开(公告)日：2017-10-17

申请号：US15230055

申请日：2016-08-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/148 ,  H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14638 ,  H01L27/14689

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

公开(公告)号：US09786755B2

公开(公告)日：2017-10-10

申请号：US14930150

申请日：2015-11-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Dominique Golanski ,  Gregory Bidal ,  Simon Jeannot

IPC: H01L21/84 ,  H01L29/423 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

CPC classification number: H01L29/42364 ,  H01L27/12 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7838 ,  H01L29/7881

Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.

公开(公告)号：US20170287806A1

公开(公告)日：2017-10-05

申请号：US15451862

申请日：2017-03-07

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Rafael Augusto Prieto Herrera ,  Jean-Philippe Colonna ,  Perceval Coudrain

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/3672 ,  H01L23/3185 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1816 ,  H01L2924/18161 ,  H01L2224/81

Abstract: An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support and a front face opposite its rear face. A block is provided for at least partially encapsulating the component above the front face of the support. The device also includes at least one thermal dissipation member having a flexible sheet having at least two portions folded onto one another while forming at least one fold between them, these portions facing one another at least partly.

公开(公告)号：US20170271470A1

公开(公告)日：2017-09-21

申请号：US15464763

申请日：2017-03-21

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Cyrille LE ROYER ,  Frederic Boeuf ,  Laurent Grenouillet ,  Louis Hutin ,  Yves Morand

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L23/535

CPC classification number: H01L29/4983 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66628

Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

公开(公告)号：US20170256625A1

公开(公告)日：2017-09-07

申请号：US15601115

申请日：2017-05-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Pierre Caubet ,  Florian Domengie ,  Carlos Augusto Suarez Segovia ,  Aurelie Bajolet ,  Onintza Ros Bengoechea

IPC: H01L29/49 ,  H01L29/40

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

公开(公告)号：US20170248543A1

公开(公告)日：2017-08-31

申请号：US15251009

申请日：2016-08-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Gaspard Hiblot

IPC: G01N27/414 ,  H01L27/12 ,  H01L29/788 ,  H01L27/06 ,  H01L29/423

CPC classification number: H01L27/0722 ,  G01N27/414 ,  G01N27/4145 ,  G01N33/49 ,  G01R19/16519 ,  H01L27/0623 ,  H01L27/0705 ,  H01L27/1207 ,  H01L29/42356

Abstract: An integrated electronic detector operates to detecting a variation in potential on an input terminal. The detector includes a MOS transistor having a drain forming an output. Variation in drain current is representative of the variation in potential. A bipolar transistor has a base forming the input terminal and a collector electrically connected to the gate of the MOS transistor. The detector has a first configuration in which the bipolar transistor is conducting and the MOS transistor is turned off. The detector has a second configuration in which the bipolar transistor is turned off and the MOS transistor is in a sub-threshold operation. Transition of the detector from the first configuration to the second configuration occurs in response to the variation in potential.