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    HIGH CAPACITY MEMORY SYSTEMS
    662.
    发明申请
    HIGH CAPACITY MEMORY SYSTEMS 有权
    高容量存储系统

    公开(公告)号：US20150089164A1

    公开(公告)日：2015-03-26

    申请号：US14386561

    申请日：2012-12-20

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

    IPC: G06F13/42 ,  G06F13/16 ,  G11C7/10

    CPC classification number: G11C8/18 ,  G06F13/161 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

    Abstract translation: 在允许每个等级的时钟分配树被允许在宽范围内漂移的多存储器存储器系统（例如，低功率存储器系统）中，通过使用引起每个寻址的技术来促进等级之间的命令的精细交错 排名适当地采样旨在该等级的命令，尽管有漂移。 执行这种“微线程”的能力提供了显着增强的存储器容量，而不牺牲单级系统的性能。 本公开提供了适于这些目的的方法，存储器控制器，存储器件和系统设计。

    Memory Controller For Selective Rank Or Subrank Access
    663.
    发明申请
    Memory Controller For Selective Rank Or Subrank Access 有权
    内存控制器，用于选择性等级或子选项访问

    公开(公告)号：US20150089163A1

    公开(公告)日：2015-03-26

    申请号：US14558517

    申请日：2014-12-02

    Applicant: Rambus Inc.

    Inventor： Craig E. Hampel ,  Frederick A. Ware

    IPC: G06F13/16

    CPC classification number: G06F13/1642 ,  G06F12/1081 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/28 ,  G06F13/4243 ,  G06F2212/656 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1075 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/10159 ,  Y02D10/14 ,  Y02D10/151 ,  Y02P70/611

    Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

    Abstract translation: 具有减小的访问粒度的存储器模块。 存储器模块包括其上具有信号线的衬底，其形成控制路径和第一和第二数据路径，并且还包括共同耦合到控制路径并分别耦合到第一和第二数据路径的第一和第二存储器件。 第一和第二存储器件包括控制电路，用于响应于第一和第二存储器访问命令，经由控制路径接收相应的第一和第二存储器访问命令并且执行第一和第二数据路径上的并发数据传输。

    Memory Controllers, Systems, and Methods Supporting Multiple Request Modes
    665.
    发明申请
    Memory Controllers, Systems, and Methods Supporting Multiple Request Modes 有权
    支持多种请求模式的内存控制器，系统和方法

    公开(公告)号：US20140297939A1

    公开(公告)日：2014-10-02

    申请号：US14305799

    申请日：2014-06-16

    Applicant: Rambus Inc.

    Inventor： Richard E. Perego ,  Frederick A. Ware

    IPC: G11C7/10

    CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

    Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

    Abstract translation: 存储器系统包括具有多个存储器 - 控制器块的存储器控​​制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。 请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。 所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。 每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

    PROCESS AUTHENTICATED MEMORY PAGE ENCRYPTION
    667.
    发明申请
    PROCESS AUTHENTICATED MEMORY PAGE ENCRYPTION 有权
    过程认证内存页加密

    公开(公告)号：US20140237261A1

    公开(公告)日：2014-08-21

    申请号：US14133383

    申请日：2013-12-18

    Applicant: RAMBUS INC.

    Inventor： Trung Am Diep ,  Pradeep Batra ,  Brian S. Leibowitz ,  Frederick A. Ware

    IPC: G06F12/14

    CPC classification number: G06F21/79 ,  G06F12/1009 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/30

    Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

    Abstract translation: 存储器控制器至少部分地基于与页面帧相关联的帧密钥来加密页面帧的内容。 所述存储器控制器至少部分地基于与第一进程相关联的第一进程密钥来生成所述帧密钥的第一加密版本，其中所述帧密钥的所述第一加密版本被存储在与所述第一进程相关联的第一存储器表中。 所述存储器控制器至少部分地基于与第二进程相关联的第二进程密钥来生成所述帧密钥的第二加密版本，其中所述帧密钥的所述第二加密版本被存储在与所述第二进程相关联的第二存储器表中， 第一进程和第二进程分别使用帧密钥的第一加密版本和帧密钥的第二加密版本共享对页面帧的访问。

    Reconfigurable Memory Controller
    668.
    发明申请
    Reconfigurable Memory Controller 有权
    可重构内存控制器

    公开(公告)号：US20140181331A1

    公开(公告)日：2014-06-26

    申请号：US14167635

    申请日：2014-01-29

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Venu Madhav Kuchibholta

    IPC: G06F3/06

    CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1694

    Abstract: Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.

    Abstract translation: 描述存储器控制器的实施例。 该存储器控制器包括电耦合到包括多个链路的通信路径的信号连接器，以及电耦合到信号连接器的接口电路。 在第一操作模式中，接口电路通过使用空中复用的通信路径与第一存储设备通信，其中在通信路径中存在专用命令/地址链路和专用数据链路。 此外，在第二操作模式中，接口电路经由使用时间复用的通信路径与第二存储设备通信，其中通信路径中的至少一些链路时间交织命令/地址信息和数据。

    Methods and Circuits for Securing Proprietary Memory Transactions
    670.
    发明申请
    Methods and Circuits for Securing Proprietary Memory Transactions 有权
    用于保护专有内存事务的方法和电路

    公开(公告)号：US20140173238A1

    公开(公告)日：2014-06-19

    申请号：US14098628

    申请日：2013-12-06

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brian S. Leibowitz ,  Pradeep Batra ,  Trung Am Diep

    IPC: G06F12/14

    CPC classification number: G06F21/85 ,  G06F21/78 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/065 ,  H04L9/12 ,  H04L2209/12 ,  H04L2209/56

    Abstract: Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.

    Abstract translation: 描述了用于保护在存储器总线上共享并存储在存储器中的数据和指令的系统和方法。 用于写入和读取通道的独立且单独定时的流密码允许写入和读取事务之间的时序变化。 数据和指令可以在通道加密之前单独加密，以进一步保护信息。 垫片发生器和相关的加密电路被共享用于读取和写入数据，并且保护地址。 加密电路可以支持可变数据宽度，并且在一些实施例中，存储器设备包括可以使用重用存储器电路来实现共享密钥算法的安全电路。

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