公开(公告)号：US20240222304A1

公开(公告)日：2024-07-04

申请号：US18148148

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Jiaqi Wu ,  Haobo Chen ,  Srinivas Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/538 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16

Abstract: Methods and apparatus to reduce solder bump bridging between two substrates. An apparatus includes a first substrate including a first bump and a second bump spaced apart from the first bump, the first bump including a first base, the second bump including a second base; and a second substrate including a third bump and a fourth bump spaced apart from the third bump, the third bump including a third base, the fourth bump including a fourth base, the first base electrically coupled to the third base by first solder, the second base electrically coupled to the fourth base by second solder, the first solder having a first volume, the second solder having a second volume, the first volume less than the second volume.

公开(公告)号：US20240222295A1

公开(公告)日：2024-07-04

申请号：US18148598

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Mahdi Mohammadighaleni ,  Joshua Stacey ,  Benjamin T. Duong ,  Thomas S. Heaton ,  Dilan Seneviratne ,  Rahul N. Manepalli

IPC: H01L23/64 ,  H01G4/20 ,  H01G4/33 ,  H01L23/00 ,  H01L23/498 ,  H05K1/16

CPC classification number: H01L23/642 ,  H01G4/206 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H05K1/162 ,  H01L2224/16235 ,  H01L2924/19041 ,  H05K2201/0175

Abstract: Embodiments described herein enable a microelectronic assembly that includes: a package substrate having a core including a solid continuous glass material with one or more capacitors in the solid continuous glass material and integrated circuit (IC) dies coupled to the package substrate. The structure of each capacitor includes a dielectric structure between two conductive structures. The dielectric structure comprises a layer of organic dielectric material between two layers of crystalline inorganic material. The crystalline inorganic material is in direct contact with one of the two conductive structures.

公开(公告)号：US20240222288A1

公开(公告)日：2024-07-04

申请号：US18090140

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： David Shia ,  Timothy Gosselin ,  Aravindha Antoniswamy ,  Sergio Antonio Chan Arguedas ,  Elah Bozorg-Grayeli ,  Johnny Cook, JR. ,  Steven Klein ,  Rick Canham

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/427 ,  H01L23/49

CPC classification number: H01L23/544 ,  H01L23/427 ,  H01L23/49 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/08113 ,  H01L2224/48229 ,  H01L2924/15165 ,  H01L2924/1711 ,  H01L2924/173 ,  H01L2924/17724 ,  H01L2924/1776

Abstract: Integrated circuit (IC) device substrates and structures for mating and aligning with sockets. An IC device may include a frame on and around a substrate, which may include glass or silicon. The frame may include an alignment feature, such as a notch or hole, to mate with a complementary keying feature of a socket. A heat spreader may be coupled to an IC die and extend beyond the substrate or be coupled to the frame. The heat spreader may include a heat pipe. The IC device may be part of an IC system with the device substrate coupled to a system substrate by a socket configured to mate to the frame.

公开(公告)号：US20240222276A1

公开(公告)日：2024-07-04

申请号：US18089877

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Tahir GHANI ,  Anand S. MURTHY ,  Wilfred GOMES

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H05K1/18

CPC classification number: H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H05K1/181 ,  H05K2201/10159

Abstract: Structures having lookup table decoders for FPGAs with high DRAM transistor density are described. In an example, an integrated circuit structure includes a plurality of fins or nanowire stacks, individual ones of the plurality of fins or nanowire stacks having a longest dimension along a first direction. A plurality of gate structures is over the plurality of fins or nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction.

公开(公告)号：US20240222238A1

公开(公告)日：2024-07-04

申请号：US18091543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/15

CPC classification number: H01L23/49811 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/81815

Abstract: An integrated circuit device substrate includes a glass substrate with a first major surface comprising a plateau region, a cavity region, and a wall between the plateau region and the cavity region. The first major surface includes thereon a first dielectric region, and the plateau region includes a plurality of conductive pillars. A second major surface of the glass substrate opposite the first major surface includes thereon a second dielectric layer, wherein the second dielectric layer includes at least one dielectric-free window underlying the cavity region.

公开(公告)号：US20240221821A1

公开(公告)日：2024-07-04

申请号：US18089886

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY

IPC: G11C11/409 ,  H01L23/522 ,  H01L23/528

CPC classification number: G11C11/409 ,  H01L23/5226 ,  H01L23/5283

Abstract: Structures having two-transistor gain cell are described. In an example, an integrated circuit structure includes a frontend device layer including a read transistor. A backend device layer is above the frontend device layer, the backend device layer including a write transistor. An intervening interconnect layer is between the backend device layer and the frontend device layer, the intervening interconnect layer coupling the write transistor of the backend device layer to the read transistor of the front-end device layer.

公开(公告)号：US20240221715A1

公开(公告)日：2024-07-04

申请号：US18090427

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Jaison FERNANDEZ ,  Sumod CHERUKKATE ,  Tarakesava Reddy KOKI ,  Adam KUPRYJANOW ,  Srikanth POTLURI

IPC: G10K11/178 ,  H04R1/10

CPC classification number: G10K11/17823 ,  G10K11/17873 ,  H04R1/1083 ,  G10K2210/1081 ,  G10K2210/30231 ,  G10K2210/3027 ,  G10K2210/3036 ,  H04R2460/01

Abstract: This disclosure describes systems, methods, and devices related to noise suppression processing. A device may establish a connection to a connected device. The device may calculate a first SNR of a first sample of a first audio stream from the connected device. The device may calculate a second SNR of a second sample of a second audio stream from a first device. The device may compare a difference of the first SNR and the second SNR to a Delta SNR threshold. The device may detect ambient noise level conditions and the Delta SNR threshold is based on the ambient noise level conditions. The device may determine whether to apply system-level preprocessing based on the comparison.

公开(公告)号：US20240220699A1

公开(公告)日：2024-07-04

申请号：US18148963

申请日：2022-12-30

Applicant: INTEL CORPORATION

Inventor： Michael Goldsmith ,  Prashant Majhi ,  Per Sverdrup ,  Chung-Ching Peng

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F2111/20

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed including at least one memory; machine-readable instructions; and processor circuitry to at least one of execute or instantiate the machine-readable instructions to: obtain a register-transfer level design defining operations of electrical circuits in first and second dice of a multi-die semiconductor package, the second die to be stacked on the first die in the multi-die semiconductor package; and select placement of a cell for a physical layout for the multi-die semiconductor package based on the register-transfer level design, the cell including a via to electrically interconnect the first die to the second die.

公开(公告)号：US20240220276A1

公开(公告)日：2024-07-04

申请号：US18090269

申请日：2022-12-28

Applicant: INTEL CORPORATION

Inventor： Atsuo Kuwahara ,  Prasanna Desai ,  Kannan Raja

IPC: G06F9/4401 ,  G06F1/3231 ,  H04W52/02

CPC classification number: G06F9/4418 ,  G06F1/3231 ,  H04W52/0229 ,  H04W52/0254

Abstract: For example, a display device may be configured to detect a proximity event based on Bluetooth (BT) signals communicated between a BT radio of the display device and a peripheral BT device. For example, the proximity event may indicate proximity of the peripheral BT device to the display device. For example, the display device may be configured to, based on the proximity event, send a proximity-based trigger signal to a computing device via a communication link between the display device and the computing device. For example, the proximity-based trigger signal may be configured to trigger a proximity-based change of an operational state of the computing device.

公开(公告)号：US20240220249A1

公开(公告)日：2024-07-04

申请号：US18147099

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Jian-Guo Chen ,  David Dougherty ,  Madihally Narasimha ,  Joseph Othmer ,  Hong Wan ,  Joseph Williams ,  Zoran Zivkovic

IPC: G06F9/30 ,  G06F30/343

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F30/343

Abstract: Techniques are disclosed for the implementation of a programmable processing array architecture that realizes vectorized processing operations for a variety of applications. Such vectorized processing operations may include digital front end (DFE) processing operations, which include finite impulse response (FIR) filter processing operations. The programmable processing array architecture provides a front-end interconnection network that generates specific data sliding time window patterns in accordance with the particular DFE processing operation to be executed. The architecture enables the processed data generated in accordance with these sliding time window patterns to be fed to a set of multipliers and adders to generate output data. The architecture supports a wide range of processing operations to be performed via a single programmable processing array platform by leveraging the programmable nature of the array and the use of instruction sets.