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公开(公告)号：US09214235B2
公开(公告)日：2015-12-15
申请号：US14046281
申请日：2013-10-04
Inventor： Hyoung Seub Rhie
IPC: H01L29/792 , G11C16/04 , H01L27/115
CPC classification number: H01L27/11582 , G11C16/0483 , G11C16/14 , H01L27/11524 , H01L27/11556 , H01L27/1157
Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.
Abstract translation: 包括阱和U形闪存单元串的闪存器件，U形闪存单元串直接构建在与阱相邻的衬底上。 U形闪存单元串包括平行于衬底的表面的一个部分，包括无连接底部传输晶体管，以及垂直于衬底表面的两个部分，其包括在电池串的第一顶部的串选择晶体管， 在单元串的第二顶部的接地选择晶体管，串选择晶体管漏极和接地选择晶体管源。
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62.发明授权Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage 有权使用正阱偏置电压和负字线电压擦除闪存器件中的存储单元的方法公开(公告)号：US09214233B2
公开(公告)日：2015-12-15
申请号：US13895591
申请日：2013-05-16
Inventor： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
CPC classification number: G11C16/14 , G11C16/02 , G11C16/0408 , G11C16/08 , G11C16/16
Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
Abstract translation: 一种非易失性存储器件，包括存储器阵列，该存储器阵列具有被组织为扇区的多个存储器单元，每个扇区具有与多个本地字线相关联的主字线，每个本地字线通过 各自的本地字线驱动电路，每个本地字线驱动电路由耦合在相应主字线和相应本地字线之间的第一MOS晶体管和耦合在相应本地字线和第一 偏置端子
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公开(公告)号：US09202578B2
公开(公告)日：2015-12-01
申请号：US14044449
申请日：2013-10-02
Inventor： Hyoung Seub Rhie
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/14
Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.
Abstract translation: 三维集成电路非易失性存储器阵列包括具有多个垂直栅极NAND存储器单元串的存储器阵列，该多个垂直栅极NAND存储器单元串形成在共享一组公共字线的衬底上的不同垂直层中，其中形成了不同的NAND存储器单元串组 在源线结构和位线结构的专用配对之间形成单独的可擦除块，其通过向擦除块擦除块的源极线结构施加擦除电压来寻址和擦除，同时向阵列中的其它源极线结构施加接地电压 以及对阵列中的位线结构的高通电压。
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公开(公告)号：US20150309867A1
公开(公告)日：2015-10-29
申请号：US14795114
申请日：2015-07-09
Inventor： Jin-Ki KIM
CPC classification number: G06F11/1044 , G06F11/1048 , G11C2029/0411 , H03M13/05 , H03M13/611
Abstract: A composite semiconductor memory device, comprising: a plurality of nonvolatile memory devices; and an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the interface device comprising an error correction coding (ECC) engine. Also, a memory system, comprising: a memory controller; and at least one composite semiconductor memory device configured for being written to and read from by the memory controller and comprising a built-in error correction coding (ECC) engine. Also, a memory system, comprising: a composite semiconductor memory device comprising a plurality of nonvolatile memory devices; and a memory controller connected to the at least one composite semiconductor memory device, for issuing read and write commands to the composite semiconductor memory device to cause data to be written to or read from individual ones of the nonvolatile memory devices; the composite semiconductor memory device providing error-free writing and reading of the data.
Abstract translation: 一种复合半导体存储器件，包括：多个非易失性存储器件; 以及连接到所述多个非易失性存储器件并且用于连接到存储器控制器的接口设备，所述接口设备包括纠错编码（ECC）引擎。 另外，一种存储器系统，包括：存储器控制器; 以及至少一个复合半导体存储器件，被配置为被存储器控制器写入和读出，并且包括内置纠错编码（ECC）引擎。 另外，一种存储系统，包括：复合半导体存储器件，其包括多个非易失性存储器件; 以及存储器控制器，连接到所述至少一个复合半导体存储器件，用于向所述复合半导体存储器件发出读取和写入命令，以使数据被写入或从所述非易失性存储器件中的各个写入; 所述复合半导体存储器件提供无错误的写入和读取数据。
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公开(公告)号：US09117685B2
公开(公告)日：2015-08-25
申请号：US14101507
申请日：2013-12-10
Inventor： Roland Schuetz
IPC: H01L25/00 , H01L25/065 , G11C29/00 , H01L23/48 , H01L25/18
CPC classification number: H01L25/0657 , G11C29/808 , H01L23/481 , H01L25/18 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
Abstract: Through silicon vias (TSVs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. TSV connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die. TSV connections to the inputs and/or outputs of a die's native circuitry may be changed. A die may be disconnected altogether from an interface that interconnects dice in the stack, or a die that was originally disconnected from such an interface may be connected to the interface.
Abstract translation: 通过堆叠多芯片集成电路封装中的硅通孔（TSV）被控制为在其正常任务模式下在封装的现场操作期间根据需要采取不同的连接配置。 可以重新配置TSV连接以以不同于例如该管芯的工厂默认连接的方式连接受影响的管芯。 可以改变与管芯本机电路的输入和/或输出的TSV连接。 芯片可以从互连堆叠中的裸片的接口完全断开，或者原本与此接口断开连接的裸片可能连接到接口。
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Patent Agency Ranking
66.发明授权Method and apparatus for reducing pool starvation in a shared memory switch 有权用于减少共享存储器交换机中的池缺乏的方法和装置公开(公告)号：US09083659B2
公开(公告)日：2015-07-14
申请号：US14097614
申请日：2013-12-05
Inventor： David A. Brown
IPC: G01R31/08 , H04L12/861 , H04L12/835 , H04L12/931 , H04L12/911 , H04L12/933 , H04L12/947
CPC classification number: H04L47/30 , H04L47/70 , H04L49/103 , H04L49/201 , H04L49/252 , H04L49/9047
Abstract: A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port. The switch includes pool select logic which selects a free buffer from the reserved pool for storing data received from an ingress port to be forwarded to the egress port. The shared memory also includes a shared pool of buffers. The shared pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the shared pool upon detecting no free buffer in the reserved pool. The shared memory may also include a multicast pool of buffers. The multicast pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the multicast pool upon detecting an IP Multicast data packet received from an ingress port.
Abstract translation: 交换机在共享存储器中包括一个保留的缓冲区池。 保留的缓冲池被保留供出口端口独占使用。 该交换机包括池选择逻辑，其从保留池中选择一个空闲缓冲区，用于存储从入口端口接收的数据以转发到出口端口。 共享内存还包括一个共享的缓冲池。 共享缓冲区池由多个出口端口共享。 池选择逻辑在检测到预留池中没有可用缓冲区时，会选择共享池中的空闲缓冲区。 共享存储器还可以包括缓冲器的多播池。 缓冲区的组播池由多个出口端口共享。 池选择逻辑在检测到从入口端口接收到的IP组播数据包时，选择多播池中的空闲缓冲区。
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公开(公告)号：US20150187706A1
公开(公告)日：2015-07-02
申请号：US14592117
申请日：2015-01-08
Inventor： Sang-Hyun YI , Young-Nam KIM
IPC: H01L23/00 , H01L23/58 , H01L23/528
CPC classification number: H01L23/562 , H01L21/8221 , H01L23/528 , H01L23/585 , H01L27/0688 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1112 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit.
Abstract translation: 包括半导体衬底，半导体衬底上的集成电路，覆盖集成电路的绝缘层和绝缘层上的多个金属线图案的半导体器件。 多个金属线图案的第一和第二相邻的金属线图案彼此间隔一个间隔，并且第一和第二相邻金属线图案中的每一个具有至少一个狭缝。
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公开(公告)号：US09003214B2
公开(公告)日：2015-04-07
申请号：US13796677
申请日：2013-03-12
Inventor： George B. Raad
CPC classification number: G06F1/3237 , G06F1/04 , G06F1/3203 , G06F1/3225 , G06F1/3234 , G06F1/324 , G06F1/3275 , G11C7/20 , G11C7/22 , G11C7/225 , G11C2207/2227 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D50/20
Abstract: The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed.
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公开(公告)号：US20150008956A1
公开(公告)日：2015-01-08
申请号：US14499275
申请日：2014-09-29
Inventor： Bruce MILLAR
CPC classification number: H03K19/0005 , G11C5/063 , G11C7/02 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C11/4093 , G11C2207/2254 , H03H7/38 , H03H17/0045 , H04L25/0278 , H04L25/028
Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.
Abstract translation: 提供了执行片外驱动（OCD）和片上终端（ODT）的系统和方法。 由晶体管组成的公共上拉网络和由晶体管组成的公共下拉网络被采用来实现这两个功能。 在驱动模式下，上拉网络被配置为当要产生“开”输出时产生校准的驱动阻抗，并且当“关”输出为“关”时，上拉网络被配置为产生校准的驱动阻抗 生成。 在终端模式中，上拉网络和下拉网络被配置为分别产生校准的上拉电阻和下拉电阻，使得它们一起形成分离终端。
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公开(公告)号：US08848511B2
公开(公告)日：2014-09-30
申请号：US14135167
申请日：2013-12-19
Inventor： Antonio Francescon , Davide Mandato
Abstract: This invention relates to a network architecture for data communication between data sources and data destinations via network nodes and at least one data concentrator. According to the invention the nodes (2, 4) are conceived to communicate with a data concentrator (1) in both directions either via a permanently operative network (8) in the multihop mode or via an occasionally operative network (5) in wireless connection with mobile user nodes (6) in the nomadic mode. Means for commutation are provided to detect faulty multihop nodes and to activate nomadic nodes instead until the fault disappears, in order to maintain the overall functionality of the network. Moreover the network according to the invention allows to share the data collected by mobile users with other mobile users, thus forming a peer-to-peer network.
Abstract translation: 本发明涉及用于经由网络节点和至少一个数据集中器的数据源和数据目的地之间的数据通信的网络架构。 根据本发明，节点（2,4）被设想为在多重模式下经由永久操作的网络（8）或经由无线连接中的偶尔操作的网络（5）在两个方向上与数据集中器（1）进行通信 移动用户节点（6）处于游牧模式。 提供换向的手段来检测故障多跳节点并激活游牧节点，直到故障消失为止，以维持网络的整体功能。 此外，根据本发明的网络允许与其他移动用户共享移动用户收集的数据，从而形成对等网络。
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