公开(公告)号：US08693163B2

公开(公告)日：2014-04-08

申请号：US12873931

申请日：2010-09-01

申请人： An-Jhih Su ,  Chi-Chun Hsieh ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng

发明人： An-Jhih Su ,  Chi-Chun Hsieh ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC分类号： H01L29/92 ,  H01L21/768

CPC分类号： H01L28/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L28/92 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

摘要翻译： 一种装置包括具有与前表面相对的前表面和后表面的基底。 电容器形成在衬底中，并包括第一电容器板; 围绕所述第一电容器板的第一绝缘层; 以及环绕所述第一绝缘层的第二电容器板。 第一电容器板，第一绝缘层和第二电容器板中的每一个从基板的前表面延伸到后表面。

公开(公告)号：US20140027900A1

公开(公告)日：2014-01-30

申请号：US13558082

申请日：2012-07-25

申请人： Tzu-Wei Chiu ,  Tzu-Yu Wang ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Hsien-Wei Chen ,  Hung-An Teng ,  Wei-Cheng Wu

发明人： Tzu-Wei Chiu ,  Tzu-Yu Wang ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Hsien-Wei Chen ,  Hung-An Teng ,  Wei-Cheng Wu

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L24/81 ,  B23K1/0016 ,  C23C14/165 ,  C23C14/34 ,  C23C18/32 ,  C23C18/42 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/10125 ,  H01L2224/114 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/119 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/8112 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00

摘要： A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

摘要翻译： 提供了用于电耦合半导体部件的凸块结构。 凸块结构包括在第一半导体部件上的第一凸块和第二半导体部件上的第二凸块。 第一凸起具有第一非平坦部分（例如，凸起的凸起），并且第二凸起具有第二非平坦部分（例如，凹形凹部）。 凸起结构还包括形成在第一和第二非平坦部分之间的焊接接头以电耦合半导体部件。

公开(公告)号：US08519512B2

公开(公告)日：2013-08-27

申请号：US11525575

申请日：2006-09-22

申请人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

发明人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

IPC分类号： H01L23/544

CPC分类号： H01L21/78 ,  H01L21/782 ,  H01L21/784 ,  H01L21/786 ,  H01L22/10 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.

公开(公告)号：US20120178252A1

公开(公告)日：2012-07-12

申请号：US13427430

申请日：2012-03-22

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L21/768

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.

摘要翻译： 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。

公开(公告)号：US08030776B2

公开(公告)日：2011-10-04

申请号：US12575078

申请日：2009-10-07

申请人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Hsien Wei Chen ,  Hsiu-Ping Wei

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Hsien Wei Chen ,  Hsiu-Ping Wei

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/053 ,  H01L23/12 ,  H01L27/10 ,  H01L29/74

CPC分类号： H01L23/522 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00

摘要： A structure includes a semiconductor substrate having semiconductor devices formed on or in the substrate. An interconnecting metallization structure is formed over and connected to the devices. The interconnecting metallization structure including at least one dielectric layer. A passivation layer is deposited over the interconnecting metallization structure and the dielectric layer. At least one metal contact pad and at least one dummy metal structure are provided in the passivation layer. The contact pad is conductively coupled to at least one of the devices. The dummy metal structure is spaced apart from the contact pad and unconnected to the contact pad and the devices.

摘要翻译： 一种结构包括具有形成在衬底上或衬底中的半导体器件的半导体衬底。 互连金属化结构形成在器件上并连接到器件。 互连金属化结构包括至少一个电介质层。 在互连金属化结构和电介质层上沉积钝化层。 在钝化层中提供至少一个金属接触焊盘和至少一个虚拟金属结构。 接触焊盘导电地耦合到至少一个设备。 虚拟金属结构与接触垫间隔开，并且不连接到接触垫和设备。

公开(公告)号：US20100207251A1

公开(公告)日：2010-08-19

申请号：US12619464

申请日：2009-11-16

申请人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Ming-Yen Chiu

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Ming-Yen Chiu

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L21/78

摘要： A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a series of alternating dummy lines that are connected through dummy vias. The dummy lines are offset from dummy lines in adjacent metal layers. Additionally, the dummy lines and dummy vias in the upper layers of the scribe line may be formed with larger dimensions than the dummy lines and dummy vias located in the lower layers.

摘要翻译： 提出了一种在分割过程中防止违约的系统和方法。 一个实施例包括位于划线区域中的虚拟金属结构。 虚拟金属结构包括通过虚拟通孔连接的一系列交替虚拟线。 伪线与相邻金属层中的虚拟线偏移。 此外，划线的上层中的虚线和虚拟通路可以形成为具有比位于下层中的虚拟线和虚拟通孔更大的尺寸。

公开(公告)号：US07714443B2

公开(公告)日：2010-05-11

申请号：US11458501

申请日：2006-07-19

申请人： Hsien-Wei Chen ,  Anbiarshy Wu ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Anbiarshy Wu ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

IPC分类号： H01L23/52

CPC分类号： H01L21/76895 ,  H01L22/34 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/30105

摘要： An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different from the pad density of the pad structure of the first interconnect layer. The pad structures of the first and second interconnect layers are connected to each other.

摘要翻译： 互连结构至少包括第一互连层和第二互连层。 第一和第二互连层中的每一个具有焊盘结构，并且每个焊盘结构具有相应的焊盘密度。 第二互连层的焊盘结构的焊盘密度不同于第一互连层的焊盘结构的焊盘密度。 第一和第二互连层的焊盘结构彼此连接。

公开(公告)号：US20090115024A1

公开(公告)日：2009-05-07

申请号：US11933931

申请日：2007-11-01

申请人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

发明人： Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC分类号： H01L23/52

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a lower dielectric layer; an upper dielectric layer over the lower dielectric layer; and a seal ring. The seal ring includes an upper metal line in the upper dielectric layer; a continuous via bar underlying and abutting the upper metal line, wherein the continuous via bar has a width greater than about 70 percent of a width of the upper metal line; a lower metal line in the lower dielectric layer; and a via bar underlying and abutting the lower metal line. The via bar has a width substantially less than a half of a width of the lower metal line.

摘要翻译： 集成电路结构包括下介电层; 在下介电层上的上电介质层; 和密封环。 密封环包括在上介电层中的上金属线; 连续的通孔条，其下面并邻接上部金属线，其中所述连续通孔条具有大于所述上部金属线宽度的约70％的宽度; 下介电层中的下金属线; 以及位于下金属线下方并邻接的通孔条。 通孔棒具有基本上小于下金属线宽度的一半的宽度。

公开(公告)号：US07449785B2

公开(公告)日：2008-11-11

申请号：US11347378

申请日：2006-02-06

申请人： Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai

发明人： Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further comprises a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.

摘要翻译： 提供半导体衬底上的焊料凸块。 焊料凸块包括其上具有顶部铜焊盘的半导体衬底，半导体衬底上的保护层和覆盖保护层的至少一个无机钝化层，第一开口露出顶部铜焊盘，其中无机钝化层具有较薄的 邻近第一开口的顶部的部分。 所述焊料凸块还包括在所述无机钝化层上的软钝化层，其具有大于所述第一开口的第二开口，沿所述第一开口和所述第二开口共形形成的凸块下金属层和形成在所述下凸块金属层上的焊料凸块 。

公开(公告)号：US20070182007A1

公开(公告)日：2007-08-09

申请号：US11347378

申请日：2006-02-06

申请人： Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai

发明人： Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further comprises a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.

摘要翻译： 提供半导体衬底上的焊料凸块。 焊料凸块包括其上具有顶部铜焊盘的半导体衬底，半导体衬底上的保护层和覆盖保护层的至少一个无机钝化层，第一开口露出顶部铜焊盘，其中无机钝化层具有较薄的 邻近第一开口的顶部的部分。 所述焊料凸块还包括在所述无机钝化层上的软钝化层，其具有大于所述第一开口的第二开口，沿所述第一开口和所述第二开口共形形成的凸块下金属层和形成在所述下凸块金属层上的焊料凸块 。