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340 条记录 (耗时 0.026 秒)

    Borderless wordline for DRAM cell
    61.
    发明授权
    Borderless wordline for DRAM cell 失效
    DRAM单元的无边界字线

    公开(公告)号：US06271555B1

    公开(公告)日：2001-08-07

    申请号：US09052403

    申请日：1998-03-31

    申请人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Wendell P. Noble, Jr.

    发明人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Wendell P. Noble, Jr.

    IPC分类号： H01L27108

    CPC分类号： H01L27/10873 ,  H01L27/10891 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S257/908

    摘要： A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline. A bitline contact contacts the source/drain region and the insulating material surrounding the active wordline to thereby make the bitline contact borderless to the wordline. A fully encased passing wordline is also provided which is spaced from and insulated from the segment gate conductor and the active wordline.

    摘要翻译： 公开了一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。 栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。 晶体管还具有具有源/漏区的单晶半导体衬底。 主动导电字线沉积在分段栅极导体的顶部并与其电接触，该字线是具有顶部和侧壁的导电材料。 电绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。 围绕有源字线的绝缘材料包括覆盖顶部并且围绕其侧壁的一部分的氮化硅，并且二氧化硅围绕有源字线的侧壁的其余部分。 位线触点接触源极/漏极区域和围绕有源字线的绝缘材料，从而使位线接触到字线。 还提供了完全封装的通过字线，其与分段栅极导体和有源字线间隔开并与之隔绝。

    Process for building borderless bitline, wordline amd DRAM structure
    62.
    发明授权
    Process for building borderless bitline, wordline amd DRAM structure 失效
    构建无边界位线，字线amd DRAM结构的过程

    公开(公告)号：US06261933B1

    公开(公告)日：2001-07-17

    申请号：US09494415

    申请日：2000-01-31

    申请人： Mark C. Hakey ,  David V. Horak ,  William H. Ma ,  Wendell P. Noble, Jr.

    发明人： Mark C. Hakey ,  David V. Horak ,  William H. Ma ,  Wendell P. Noble, Jr.

    IPC分类号： H01L213205

    CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10891

    摘要： It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material. Insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. A bitline contact contacting the insulating material surrounds the wordline contact in the source/drain region to thereby make the bitline contact borderless to the wordline.

    摘要翻译： 本发明的一个特征是，最小尺寸字线连接大致最小尺寸的单独栅极段，位线接触与字线无边界。本发明的另一个目的是提供具有单独的段栅极导体 以及具有位线接触对该字线无边界的极小尺寸的栅极连接器。一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。 栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。 晶体管还包括具有源/漏区的单晶半导体衬底。 活动导电字线沉积在分段栅极导体的顶部并且电接触，其中字线是导电材料。 绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。 接触绝缘材料的位线接触器围绕源极/漏极区域中的字线触点，从而使位线接触到字线。

    Method for forming a horizontal surface spacer and devices formed thereby
    65.
    发明授权
    Method for forming a horizontal surface spacer and devices formed thereby 失效
    用于形成水平表面间隔物的方法和由此形成的装置

    公开(公告)号：US6100172A

    公开(公告)日：2000-08-08

    申请号：US182173

    申请日：1998-10-29

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

    IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/768 ,  H01L21/822 ,  H01L29/78 ,  H01L21/22 ,  H01L21/425 ,  H01L21/8234

    CPC分类号： H01L29/66613 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76895 ,  H01L21/822 ,  H01L29/7835

    摘要： The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

    摘要翻译： 本发明提供一种用于在水平表面上形成自对准间隔物的方法，同时从垂直表面移除间隔物材料。 优选的方法使用可以通过使用植入物使其不溶于显影剂的抗蚀剂。 通过在具有垂直和水平表面的基底上保形地沉积抗蚀剂，植入抗蚀剂并显影抗蚀剂，在保持在水平表面上的同时将抗蚀剂从垂直表面上除去。 因此，当从垂直表面移除间隔物材料时，在水平表面上形成自对准间隔物。 然后可以将该水平表面间隔件用于进一步制造。 优选的方法可以用于许多不同的工艺，其中存在需要对衬底的垂直和水平表面进行差异化处理。

    Dual damascene dual alignment interconnect scheme
    68.
    发明授权
    Dual damascene dual alignment interconnect scheme 有权
    双镶嵌双对准互连方案

    公开(公告)号：US08803321B2

    公开(公告)日：2014-08-12

    申请号：US13490542

    申请日：2012-06-07

    申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L23/535 ,  H01L21/283

    CPC分类号： H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

    摘要翻译： 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 此后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的电介质材料的选择性蚀刻去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制的通孔腔，并沿着宽度方向 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。

    Low-profile local interconnect and method of making the same
    69.
    发明授权
    Low-profile local interconnect and method of making the same 有权
    薄型局部互连和制作相同的方法

    公开(公告)号：US08754483B2

    公开(公告)日：2014-06-17

    申请号：US13169081

    申请日：2011-06-27

    申请人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Charles W. Koburger, III ,  Chih-Chao Yang

    IPC分类号： H01L29/788

    CPC分类号： H01L21/76895 ,  H01L21/823475 ,  H04L45/58 ,  H04L49/15 ,  H04L49/45

    摘要： Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.

    摘要翻译： 本发明的实施例提供一种结构。 该结构包括多个场效应晶体管，其具有形成在半导体衬底顶部上的栅极叠层，该栅叠层具有形成在其侧壁上的隔离层; 以及直接形成在半导体衬底的顶部上并将多个场效应晶体管之一的至少一个源极/漏极互连到多个场效应中的另一个的至少一个源极/漏极的一个或多个导电触头 晶体管，其中所述一个或多个导电触点是具有低于所述栅极堆叠的高度的高度的低轮廓局部互连的一部分。