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    Wafer Level Packaging Using Blade Molding
    64.
    发明申请
    Wafer Level Packaging Using Blade Molding 审中-公开
    使用刀片成型的晶圆级包装

    公开(公告)号：US20110316201A1

    公开(公告)日：2011-12-29

    申请号：US12822880

    申请日：2010-06-24

    Applicant: Lin-Chih Huang ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

    Inventor： Lin-Chih Huang ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

    IPC: B06B1/00 ,  H01L21/56 ,  B29C45/07

    CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L24/94 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

    Abstract: In accordance with an embodiment, a molding apparatus comprises a screen having a planar top surface; a recess in the screen and extending below the planar top surface; a blade capable of traversing the planar top surface; and a molding compound applicator. Another embodiment is a method for molding. The method comprises providing a substrate in a confined volume with an open top surface, applying molding compound in the confined volume, and traversing the open top surface with a blade thereby forming the molding compound to have a planar surface that is co-planar with the open top surface. The substrate has at least one semiconductor die adhered to the substrate.

    Abstract translation: 根据实施例，成型设备包括具有平坦顶表面的筛网; 屏幕中的凹槽并在平面顶表面下方延伸; 能够穿过平面顶表面的刀片; 和模塑料涂布器。 另一实施例是一种模制方法。 该方法包括在约束体积中提供具有敞开顶部表面的基底，在约束体积中施加模塑料，并用刀片横穿开放的顶部表面，从而形成模制化合物以具有与该平坦表面共面的平坦表面 开顶表面。 衬底具有至少一个半导体管芯粘附到衬底上。

    Multiple-Gate Transistors with Reverse T-Shaped Fins
    67.
    发明申请
    Multiple-Gate Transistors with Reverse T-Shaped Fins 有权
    具有反向T形鳍的多栅极晶体管

    公开(公告)号：US20100163842A1

    公开(公告)日：2010-07-01

    申请号：US12345332

    申请日：2008-12-29

    Applicant: Li-Shyue Lai ,  Jing-Cheng Lin

    Inventor： Li-Shyue Lai ,  Jing-Cheng Lin

    IPC: H01L29/15 ,  H01L21/20

    CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

    Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

    Abstract translation: 形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。 外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。 水平板的底部接触半导体衬底。 该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。

    Ultra-Shallow Junctions using Atomic-Layer Doping
    68.
    发明申请
    Ultra-Shallow Junctions using Atomic-Layer Doping 有权
    使用原子层掺杂的超浅连接

    公开(公告)号：US20100065924A1

    公开(公告)日：2010-03-18

    申请号：US12211464

    申请日：2008-09-16

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/66636 ,  H01L21/2254 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/49 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    Abstract: A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing sides of the gate stack. The substrate may be recessed prior to forming the atomic layer and the recess may be filled by an epitaxial process. The depositing, annealing, and, if used, epitaxial growth may be repeated a plurality of times to achieve the desired junctions. Source/drain regions are also provided on opposing sides of the gate stack.

    Abstract translation: 提供半导体器件和制造方法。 基板上形成有栅叠层。 通过沉积掺杂剂的原子层并执行退火来形成超浅结，以将掺杂剂扩散到栅叠层的相对侧上的衬底中。 衬底可以在形成原子层之前被凹进，并且凹槽可以通过外延工艺填充。 可以重复沉积，退火和（如果使用）外延生长以实现所需的结。 源极/漏极区域也设置在栅极堆叠的相对侧上。

    Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materials
    69.
    发明授权
    Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materials 有权
    原子层沉积氮化钽层，以提高铜结构和上覆材料之间的粘附力

    公开(公告)号：US07202162B2

    公开(公告)日：2007-04-10

    申请号：US10420311

    申请日：2003-04-22

    Applicant: Jing-Cheng Lin ,  Chao-Hsien Peng ,  Shau Lin Shue ,  Mong Song Liang

    Inventor： Jing-Cheng Lin ,  Chao-Hsien Peng ,  Shau Lin Shue ,  Mong Song Liang

    IPC: H01L21/4763

    CPC classification number: H01L21/76849 ,  H01L21/28562

    Abstract: A process for improving the adhesion between an underlying copper structure, and overlying materials and structures, has been developed. The process features formation of a tantalum nitride layer on a copper structure, wherein the copper structure is located in a damascene type opening. To obtain the maximum adhesion benefit the tantalum nitride layer is formed via an atomic deposition layer procedure, performed at specific deposition conditions. The adhesion between the underlying copper structure and overlying materials such as a silicon nitride etch stop layer, as well the adhesion between the lower level copper structure and overlying upper level metal interconnect structures, is improved as a result of the presence of the atomic layer deposited tantalum nitride layer.

    Abstract translation: 已经开发了用于改善底层铜结构和上覆材料和结构之间的粘合性的方法。 该方法特征是在铜结构上形成氮化钽层，其中铜结构位于镶嵌型开口中。 为了获得最大的附着效益，通过在特定沉积条件下进行的原子沉积层程序形成氮化钽层。 底层铜结构和上覆材料（例如氮化硅蚀刻停止层）之间的粘附以及下层铜结构和上层金属互连结构之间的粘附性得到改善，原因在于沉积的原子层的存在 氮化钽层。

    Method of forming multilayer diffusion barrier for copper interconnections
    70.
    发明授权
    Method of forming multilayer diffusion barrier for copper interconnections 有权
    形成铜互连多层扩散阻挡层的方法

    公开(公告)号：US06969675B2

    公开(公告)日：2005-11-29

    申请号：US10942355

    申请日：2004-09-16

    Applicant: Jing-Cheng Lin

    Inventor： Jing-Cheng Lin

    IPC: H01L21/768 ,  H01L21/4763

    CPC classification number: H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

    Abstract translation: 本发明的一般目的是提供一种改进的制造方法，该方法是在单和双镶嵌互连沟槽/接触通孔加工中具有以下结构的W / WSiN / WN结构的改进的铜金属扩散阻挡层的形成 微米节点用于MOSFET和CMOS应用。 扩散阻挡层是通过沉积氮化钨底层，然后沉积原位SiH 4 / NH 3或SiH 4 H / 浸泡形成WSiN层，并沉积钨的最终顶层。 本发明用于在用于逻辑和存储器应用的MOSFET和CMOS器件的制造中制造可靠的金属互连和接触孔，并且形成的铜扩散阻挡层W / WSiN / WN在400℃下通过严格的阻挡热可靠性测试 在400℃的严格的阻隔热可靠性试验期间，纯单层阻挡层，即单层WN，表现出铜冲穿或铜尖峰。

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