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    System and method for through silicon via yield
    2.
    发明授权
    System and method for through silicon via yield 有权
    通过硅产量的系统和方法

    公开(公告)号：US09153506B2

    公开(公告)日：2015-10-06

    申请号：US13542896

    申请日：2012-07-06

    Applicant: Chien Rhone Wang ,  Kewei Zuo ,  Chen-Hua Yu ,  Jing-Cheng Lin ,  Yen-Hsin Liu

    Inventor： Chien Rhone Wang ,  Kewei Zuo ,  Chen-Hua Yu ,  Jing-Cheng Lin ,  Yen-Hsin Liu

    IPC: G06F19/00 ,  H01L21/66 ,  H01L21/768

    CPC classification number: H01L22/20 ,  H01L21/76898 ,  H01L22/12

    Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.

    Abstract translation: 本公开提供了用于形成具有一个或多个贯穿硅通孔（TSV）特征的IC结构的集成电路（IC）制造方法的一个实施例。 IC制作方法包括执行多个处理步骤; 从多个处理步骤收集物理计量数据; 基于所述物理测量数据从所述多个处理步骤收集虚拟测量数据; 基于物理测量数据和虚拟测量数据，为IC结构生成产量预测; 以及基于所述产量预测在较早的处理步骤中识别动作。

    End Point Detection in Grinding
    7.
    发明申请
    End Point Detection in Grinding 有权
    研磨中的终点检测

    公开(公告)号：US20130115854A1

    公开(公告)日：2013-05-09

    申请号：US13290879

    申请日：2011-11-07

    Applicant: Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

    Inventor： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

    IPC: B24B49/10

    CPC classification number: H01L22/26 ,  B24B7/228 ,  B24B37/013 ,  B24B49/10 ,  H01L22/12 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity.

    Abstract translation: 执行磨削的方法包括：选择用于晶片研磨工艺的目标轮加载，以及对晶片进行研磨处理。 随着研磨过程的进行，测量研磨过程的轮载荷。 在达到目标轮加载后停止研磨过程。 该方法或者包括选择晶片研磨过程的目标反射率，以及对晶片进行研磨处理。 随着研磨过程的进行，测量从晶片表面反射的光的反射率。 在一个反射率达到目标反射率之后停止研磨过程。

    Depletion-free MOS using atomic-layer doping
    8.
    发明授权
    Depletion-free MOS using atomic-layer doping 有权
    使用原子层掺杂的无耗氧MOS

    公开(公告)号：US08395221B2

    公开(公告)日：2013-03-12

    申请号：US12854638

    申请日：2010-08-11

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L21/70

    CPC classification number: H01L21/823842 ,  H01L21/2254 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/6659

    Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.

    Abstract translation: 提供半导体器件和制造方法。 介电层形成在衬底上，并且在介电层上形成未掺杂的第一含硅层。 原子层掺杂用于掺杂未掺杂的含硅层。 在第一含硅层上形成第二含硅层。 该过程可以扩展到包括在同一晶片上形成PMOS和NMOS器件。 例如，在原子层掺杂之前，第一含硅层可以在PMOS区中减薄。 在NMOS区域中，去除第一含硅层的掺杂部分，使得NMOS中的第一含硅层的剩余部分未掺杂。 此后，可以使用另一种原子层掺杂工艺将NMOS区域中的第一含硅层掺杂到不同的导电类型。 可以形成掺杂到相应导电类型的第三含硅层。

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