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    High density three dimensional semiconductor die package
    61.
    发明申请
    High density three dimensional semiconductor die package 有权
    高密度三维半导体芯片封装

    公开(公告)号：US20070096266A1

    公开(公告)日：2007-05-03

    申请号：US11264889

    申请日：2005-11-02

    申请人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

    发明人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

    IPC分类号： H01L23/495

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/143 ,  G11C8/12 ,  H01L21/485 ,  H01L23/5382 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.

    摘要翻译： 公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如在带自动焊接工艺中使用的聚酰亚胺带。 带可以具有多个重复图案的迹线和形成在其上的接触垫。 每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在将图案从基板切割成对准和堆叠之后将一个图案的迹线粘合到另一图案的迹线。 诸如闪速存储器和控制器管芯的半导体管芯安装在衬底上各个图案的迹线上。 为了使控制器裸片独特地寻址堆叠中的特定闪存芯片，支持存储芯片的每个衬底上的一组迹线被用作地址引脚，并相对于其它衬底的迹线的布局以独特的布局冲压。 通过在基板上提供具有唯一的地址迹线布局的每个闪速存储器半导体管芯，每个存储管芯可以被控制器管芯选择性地寻址。

    High density three dimensional semiconductor die package
    62.
    发明授权
    High density three dimensional semiconductor die package 有权
    高密度三维半导体芯片封装

    公开(公告)号：US07663216B2

    公开(公告)日：2010-02-16

    申请号：US11264889

    申请日：2005-11-02

    申请人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

    发明人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

    IPC分类号： H01L23/02

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/143 ,  G11C8/12 ,  H01L21/485 ,  H01L23/5382 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.

    摘要翻译： 公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如在带自动焊接工艺中使用的聚酰亚胺带。 带可以具有多个重复图案的迹线和形成在其上的接触垫。 每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在将图案从基板切割成对准和堆叠之后将一个图案的迹线粘合到另一图案的迹线。 诸如闪速存储器和控制器管芯的半导体管芯安装在衬底上各个图案的迹线上。 为了使控制器裸片独特地寻址堆叠中的特定闪存芯片，支持存储芯片的每个基板上的一组迹线用作地址引脚，并相对于其它基板的迹线的布局以独特的布局冲压。 通过在基板上提供具有唯一的地址迹线布局的每个闪速存储器半导体管芯，每个存储管芯可以被控制器管芯选择性地寻址。

    METHODS OF FORMING A SINGLE LAYER SUBSTRATE FOR HIGH CAPACITY MEMORY CARDS
    66.
    发明申请
    METHODS OF FORMING A SINGLE LAYER SUBSTRATE FOR HIGH CAPACITY MEMORY CARDS 有权
    形成高容量存储卡的单层基板的方法

    公开(公告)号：US20080081455A1

    公开(公告)日：2008-04-03

    申请号：US11538220

    申请日：2006-10-03

    申请人： Cheemen Yu ,  Hem Takiar ,  Chih-Chin Liao

    发明人： Cheemen Yu ,  Hem Takiar ,  Chih-Chin Liao

    IPC分类号： H01L21/44

    CPC分类号： H01L21/4846 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/48091 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/00014

    摘要： Methods of forming a semiconductor package including a single-sided substrate are disclosed. In a first embodiment of the present invention, a substrate may include a conductive layer on a top surface of the substrate, i.e., on the same side of the substrate as where the die are mounted. In a second embodiment of the present invention, a substrate may include a conductive layer on a bottom of the substrate, i.e., on the opposite side of the substrate as where the die are mounted.

    摘要翻译： 公开了形成包括单面基板的半导体封装的方法。 在本发明的第一实施例中，衬底可以在衬底的顶表面上，即在衬底的与安装裸片相同的一侧上包括导电层。 在本发明的第二实施例中，衬底可以包括在衬底的底部上的导电层，即衬底的安装模具的相反侧。