公开(公告)号：US06498752B1

公开(公告)日：2002-12-24

申请号：US09940159

申请日：2001-08-27

申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee

发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee

IPC分类号： G11C1606

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/3459

摘要： The present invention discloses a novel method for erasing an ETOX type and an AND type NOR flash memory arrays. The operations of the methods includes block erase which increases the Vt of the memory cell, block erase verify to check if the Vt of the erased cell is greater than a predetermined voltage Vtoff, page reverse program which reduces the Vt of the memory cell below a predetermine voltage Vtmax, reverse program verify which checks that the Vt of the memory cell is below Vtmax, page correction which corrects the Vt of cells on a page basis to be above a predetermined voltage Vtmin, and correction verify which checks that the Vt of the memory cells is above Vtmin. According to the present invention, the erase operation is performed to increase the Vt of erased cells by applying the positive high voltages to the selected word lines with bit lines and source lines grounded. The reverse program operation is performed to decrease the Vt of erased cells by applying the negative high voltage to the selected word lines with the source lines and bit lines grounded. For the ETOX cell an FN tunneling scheme is utilized for the Erase operation and CHE for the correction operation. The AND cell uses FN tunneling for both erase and correction operations.

摘要翻译： 本发明公开了一种用于擦除ETOX型和AND型NOR闪存阵列的新方法。 方法的操作包括增加存储器单元的Vt的块擦除，块擦除验证以检查擦除单元的Vt是否大于预定电压Vtoff，页面反向程序，其将存储器单元的Vt减小到低于 预先确定电压Vtmax，反向程序验证哪个检查存储器单元的Vt低于Vtmax，将页面上的单元格的Vt校正为高于预定电压Vtmin的页面校正，以及校正验证哪个检查Vt 存储单元高于Vtmin。 根据本发明，执行擦除操作以通过将位线和源极线接地的正高电压施加到所选择的字线来增加擦除单元的Vt。 执行反向编程操作以通过将源极线和位线接地来对所选择的字线施加负高电压来减小擦除单元的Vt。 对于ETOX单元，使用FN隧道方案进行擦除操作和CHE进行校正操作。 AND单元使用FN隧道进行擦除和校正操作。

公开(公告)号：US06275417B1

公开(公告)日：2001-08-14

申请号：US09680651

申请日：2000-10-06

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C1604

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C11/5621 ,  G11C16/26 ,  G11C2211/5634

摘要： Data stored in multi-level memory cells is rapidly read out with high resolution by generating and coupling a predetermined and preferably low number of large magnitude jump-like voltage changes to the control gates of the memory cells. The magnitude of the jumps can be a substantial fraction of the power supply level and will be many times the &Dgr;Vt levels associated with the memory cells, e.g., the control gate voltage changes in jump-steps from say 4 V to 6 V to 8 V. Use of a low number of jump-steps (e.g., two or three) reduces read out time by permitting read out of a plurality of Vt levels during a given control voltage magnitude. Further, use of large but different magnitude control gate voltages provides good read out resolution over the range of Vt values. Reference cells are provided to improve tracking, and DRAM-type sense amplifiers are provided to maintain high noise immunity.

摘要翻译： 存储在多电平存储单元中的数据通过产生并将预定的和优选的低数量的大幅度的类似跳变的电压变化耦合到存储器单元的控制栅极而以高分辨率快速读出。 跳跃的幅度可以是电源电平的很大一部分，并且将是与存储器单元相关联的DELTAVt电平的许多倍，例如，控制栅极电压在从4V变为6V至8V的跳变步长 使用低数量的跳跃步骤（例如，两个或三个）通过允许在给定的控制电压幅度期间读出多个Vt电平来减少读出时间。 此外，使用大但不同幅度的栅极电压在Vt值的范围内提供良好的读出分辨率。 提供参考单元以改善跟踪，并且提供DRAM型读出放大器以保持高抗噪声性。

公开(公告)号：US5848000A

公开(公告)日：1998-12-08

申请号：US819323

申请日：1997-03-18

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C8/10 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  H01L27/115 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413 ,  G11C16/3431 ,  G11C8/10 ,  G11C8/12 ,  H01L27/115 ,  G11C16/24 ,  G11C2211/5642 ,  G11C2216/20 ,  G11C7/18 ,  G11C8/00

摘要： A flash memory address decoder includes a plurality of voltage terminals to receive a plurality of voltages, an address terminal to receive a plurality of address signals and a procedure terminal to receive a procedure signal. A block decoder is coupled to the address terminal and configured to decode a portion of the address signals to provide a block select signal. A wordline decoder is coupled to the address terminal and configured to decode a portion of the address signals to provide a wordline select signal. A wordline selector circuit is coupled to the block decoder and the wordline decoder and configured to receive the block select signal and the wordline select signal and to activate addressed wordlines, where the wordline selector is configured to selectively activate addressed wordlines in the flash transistor array and to provide at least two different operational voltages simultaneously on different wordlines in the flash transistor array to accomplish a predetermined procedure responsive to the procedure signal. In one embodiment, a the address decoder includes a latch structure that latches addressed wordlines and provides operational voltages to the wordlines. In another embodiment, the block decoder and wordline decoder include latch structures that latch the block select signal and the wordline select signal to provide operational voltages to the wordline selector. Advantages of the invention include high accuracy and flexibility to read, erase and program the flash memory.

摘要翻译： 闪存地址解码器包括多个用于接收多个电压的电压端子，用于接收多个地址信号的地址端子和用于接收过程信号的过程终端。 块解码器耦合到地址终端并且被配置为对部分地址信号进行解码以提供块选择信号。 字线解码器耦合到地址终端，并且被配置为对地址信号的一部分进行解码以提供字线选择信号。 字线选择器电路耦合到块解码器和字线解码器并且被配置为接收块选择信号和字线选择信号并激活寻址字线，其中字线选择器被配置为选择性地激活闪存晶体管阵列中的寻址字线， 以在闪光晶体管阵列中的不同字线上同时提供至少两个不同的操作电压，以响应于过程信号来完成预定的过程。 在一个实施例中，地址解码器包括锁存寻址字线并向字线提供工作电压的锁存结构。 在另一个实施例中，块解码器和字线解码器包括锁存块选择信号和字线选择信号以向字线选择器提供工作电压的锁存结构。 本发明的优点包括读取，擦除和编程闪存的高精度和灵活性。

公开(公告)号：US5822252A

公开(公告)日：1998-10-13

申请号：US676066

申请日：1996-07-05

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  H01L27/115 ,  G11C16/00

CPC分类号： G11C16/3413 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C8/08 ,  G11C8/10 ,  H01L27/115 ,  G11C16/24 ,  G11C2211/5642 ,  G11C2211/5644 ,  G11C2216/20 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14

摘要： The invention provides a flash memory and decoder with overerase repair that can provide three word line voltages to overcome the overerased problems. The wordline decoder includes a wordline latch that provides a high flexibility of erasing size so that single/multiple sub-wordlines, single/multiple wordlines, single/multiple block, and whole array can be erased simultaneously. An exemplary embodiment of a flash memory wordline decoder that can provide three voltages includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes a plurality of latches coupled to the wordlines and configured to latch the wordlines and to provide one of a plurality of operational voltages on the wordlines to accomplish a predetermined operation responsive to the procedure signal. The plurality of voltage terminals are configured in a way that the high voltage required for erasure or for programming needs not be discharged in verification. Another exemplary embodiment provides a wordline decoder that provides three wordline voltages for verification and repairing, and also for erasure. Advantages of the invention include available full verifications for erasure, repairing and programming, tight cell threshold distribution, high efficiency repairing, no discharging the high voltage cells in verifications, full range verification voltages.

摘要翻译： 本发明提供了具有过度修复的闪存和解码器，其可以提供三个字线电压以克服过度存在的问题。 字线解码器包括字线锁存器，其提供擦除大小的高灵活性，使得可以同时擦除单个/多个子字线，单个/多个字线，单个/多个块和整个阵列。 可以提供三个电压的闪存字线解码器的示例性实施例包括多个用于接收多个电压的电压端子，多个地址端子以接收多个地址信号，接收过程信号的过程终端，以及 适于耦合到一组闪存晶体管的多个输出字线。 字线解码器电路被配置为对地址信号进行解码，并且包括耦合到字线的多个锁存器，并被配置为锁存字线并且在字线上提供多个工作电压中的一个，以响应于过程信号来完成预定的操作 。 多个电压端子被配置为在验证中不需要消除擦除或编程所需的高电压。 另一示例性实施例提供一种字线解码器，其提供用于验证和修复的三个字线电压，并且还用于擦除。 本发明的优点包括用于擦除，修复和编程的可用的完整验证，紧密的单元阈值分布，高效率修复，在验证中不排放高电压单元，全范围验证电压。

公开(公告)号：US20240233822A9

公开(公告)日：2024-07-11

申请号：US18489844

申请日：2023-10-18

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

摘要： Various 3D memory cells, array structures, and processes are disclosed. In an embodiment, a 3D memory cell structure includes a vertical conductor core, an insulator surrounding the vertical conductor core, a semiconductor layer surrounding the insulator, charge trapping layers surrounding the semiconductor layer, and a word line layer surrounding at least a portion of the charge trapping layers.

公开(公告)号：US20240135992A1

公开(公告)日：2024-04-25

申请号：US18489844

申请日：2023-10-17

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

摘要： Various 3D memory cells, array structures, and processes are disclosed. In an embodiment, a 3D memory cell structure includes a vertical conductor core, an insulator surrounding the vertical conductor core, a semiconductor layer surrounding the insulator, charge trapping layers surrounding the semiconductor layer, and a word line layer surrounding at least a portion of the charge trapping layers.

公开(公告)号：US11723288B2

公开(公告)日：2023-08-08

申请号：US17209107

申请日：2021-03-22

申请人： Fu-Chang Hsu ,  Kevin Hsu

发明人： Fu-Chang Hsu ,  Kevin Hsu

IPC分类号： G06N10/00 ,  H10N60/10 ,  H03K3/38 ,  H10N69/00

CPC分类号： H10N60/11 ,  G06N10/00 ,  H03K3/38 ,  H10N60/128 ,  H10N69/00

摘要： A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.

公开(公告)号：US10720215B2

公开(公告)日：2020-07-21

申请号：US16246378

申请日：2019-01-11

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C11/4091 ,  G11C11/4093 ,  G11C16/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/404

摘要： Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming. A method is provided for multiple-page programming of an array having a block that includes page groups and each page group includes cell strings that form pages. The method includes deactivating drain select gates (DSGs) and source select gates (SSG), applying a programming voltage to a selected word line, and applying a middle high voltage to unselected word lines. The method also includes repeating multiple programming operations while maintaining the word line voltage levels from a first programming operation to a last programming operation. Each programming operation includes loading data onto bit lines and pulsing a drain select gate associated with a selected page group to load the data into a selected page of the selected page group.

公开(公告)号：US10553293B2

公开(公告)日：2020-02-04

申请号：US16138897

申请日：2018-09-21

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C16/34 ,  H01L49/02 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/1157

摘要： A 3D NAND array with divided string architecture. In one aspect, an apparatus includes a plurality of charge storing devices connected to form a cell string. The apparatus also includes one or more internal select gates connected between selected charge storing devices in the cell string. The one or more internal select gates divide the cell string into two or more segments of charge storing devices. Selectively enabling and disabling the one or more internal select gates during programming operates to isolate one or more selected segments to reduce program-disturb to remaining segments. In another embodiment, a method is provided for programming a memory cell of a cell string having internal select gates that isolate the memory cell to reduce the effects of program-disturb. In another embodiment, multiple memory cells of a cell string having internal select gates are programmed with reduced program-disturb.

公开(公告)号：US20190244666A1

公开(公告)日：2019-08-08

申请号：US16265810

申请日：2019-02-01

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： G11C14/00

CPC分类号： G11C14/0072 ,  G11C11/412 ,  G11C11/419 ,  G11C14/0081 ,  G11C14/009

摘要： Methods and apparatus for memory cells that combine static random-access memory and non-volatile memory. In an exemplary embodiment, a memory cell is provided that includes a static random-access memory (SRAM) cell having Q and QB nodes and a non-volatile memory (NVM) array having a plurality of NVM cells. Each NVM cell comprises a memory element and a selector. The memory cell also includes select gates that selectively couple at least one of the Q and QB nodes to the plurality of NVM cells.