公开(公告)号：US09552992B2

公开(公告)日：2017-01-24

申请号：US14634483

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Min-Gyu Sung ,  Chanro Park ,  Ruilong Xie

IPC: H01L21/28 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/517

Abstract: Co-fabricating non-planar (i.e., three-dimensional) semiconductor devices with different threshold voltages includes providing a starting semiconductor structure, the structure including a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, at least two gate structures encompassing a portion of the raised structures, each gate structure including a gate opening lined with dielectric material and partially filled with work function material, a portion of the work function material being recessed. The co-fabrication further includes creating at least one conformal barrier layer in one or more and less than all of the gate openings, filling the gate openings with conductive material, and modifying the work function of at least one and less than all of the filled gate structures.

Abstract translation: 共同制造具有不同阈值电压的非平面（即，三维）半导体器件包括提供起始半导体结构，该结构包括半导体衬底，耦合到衬底的多个凸起半导体结构，至少两个栅极结构， 每个栅极结构包括一个衬有介电材料并部分填充有功函材料的栅极开口，一部分功函材料被凹入。 共同制造还包括在一个或多个且少于所有的栅极开口中产生至少一个共形阻挡层，用导电材料填充栅极开口，以及修改至少一个且小于所有填充的栅极开口的功函数 门结构。

公开(公告)号：US09543215B2

公开(公告)日：2017-01-10

申请号：US14691233

申请日：2015-04-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Steven John Bentley ,  Chanro Park

IPC: H01L21/8238 ,  H01L29/167 ,  H01L21/324 ,  H01L29/10 ,  H01L21/308 ,  H01L21/225

CPC classification number: H01L21/823821 ,  H01L21/2253 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1083

Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).

Abstract translation: 减少由于短路效应引起的三维半导体器件漏电的方法包括提供起始半导体结构，该结构包括具有n型器件区域和p型器件区域的半导体衬底，p型 器件区域，其包括p型半导体材料的上层，两个区域上的硬掩模层，以及用于在每个区域中构图至少一个翅片的结构上的掩模。 该方法还包括在起始半导体结构的每个区域中形成部分散热片，在该结构上形成共形衬垫，在每个区域中产生穿通停止（PTS），使得每个PTS扩散穿过顶部 并且从部分翅片在每个区域中产生全鳍。

公开(公告)号：US09425103B2

公开(公告)日：2016-08-23

申请号：US14560102

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Sean Xuan Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L27/088

CPC classification number: H01L21/823468 ,  H01L21/02181 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities.

Abstract translation: 一种涉及在第一和第二替换栅腔中形成高k栅极绝缘层，功函数调整金属层和金属保护层的方法，其中金属保护层形成为夹住第一栅极腔 同时使第二栅极腔部分未填充，在第二栅极腔的未填充部分中形成第一体导电金属层，基本上除去第一栅极腔中的所有金属保护层，同时留下金属的一部分 在所述第二栅极腔中形成保护层，在所述第一和第二替代栅极腔内形成第二导电金属层，使所述导电金属层凹陷，以分别在所述第一和第二替换栅极腔中限定第一和第二栅极盖腔， 以及在所述第一和第二栅极盖腔内形成栅极盖层。

公开(公告)号：US20160099333A1

公开(公告)日：2016-04-07

申请号：US14967797

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hoon Kim ,  Kisik Choi ,  Chanro Park

IPC: H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.

公开(公告)号：US09263446B1

公开(公告)日：2016-02-16

申请号：US14511286

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: One illustrative method disclosed herein includes, among other things, forming a shared gate cavity that spans across an isolation region and is positioned above first and second active regions, forming at least one layer of material in the shared gate cavity above the first and second active regions and above the isolation region, forming a first masking layer that covers portions of the shared gate cavity positioned above the first and second active regions while exposing a portion of the shared gate cavity positioned above the isolation region, with the first masking layer in position, performing at least one first etching process to remove at least a portion of the at least one layer of material in the exposed portion of the shared gate cavity above the isolation region, and removing the first masking layer.

Abstract translation: 本文公开的一种说明性方法尤其包括形成跨越隔离区并且位于第一和第二有源区上方的共享栅极腔，在第一和第二有源区上方的共享栅极腔中形成至少一层材料 区域并且在隔离区域上方，形成第一掩模层，其覆盖位于第一和第二有源区域上方的共享栅极腔的部分，同时暴露位于隔离区域上方的共享栅极腔的一部分，其中第一掩模层位于 执行至少一个第一蚀刻工艺以去除所述隔离区域上方的所述共享栅腔的所述暴露部分中的所述至少一层材料的至少一部分，以及去除所述第一掩模层。

公开(公告)号：US09190488B1

公开(公告)日：2015-11-17

申请号：US14458633

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/285

CPC classification number: H01L27/0922 ,  H01L21/28026 ,  H01L21/2807 ,  H01L21/283 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/105 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/772 ,  H01L29/7833 ,  H01L29/785

Abstract: One method disclosed includes forming a replacement gate structure for a device. The method includes forming a gate cavity above a semiconductor substrate. The method further includes forming a first bulk metal layer in the gate cavity above a work function metal layer. The method further includes forming a conductive etch stop layer in the gate cavity above the first bulk metal layer. The method further includes forming a second bulk metal layer in the gate cavity above the conductive etch stop layer. The method further includes performing at least one etching process to recess the first and second bulk metal layers selectively relative to the conductive etch stop layer. The method further includes performing at least one etching process to recess at least the conductive etch stop layer.

Abstract translation: 公开的一种方法包括形成用于装置的替换栅极结构。 该方法包括在半导体衬底上形成栅腔。 该方法还包括在功函数金属层上方的栅腔中形成第一块体金属层。 该方法还包括在第一体金属层上方的栅极空腔中形成导电蚀刻停止层。 该方法还包括在导电蚀刻停止层上方的栅腔中形成第二体金属层。 该方法还包括执行至少一个蚀刻工艺，以相对于导电蚀刻停止层选择性地凹入第一和第二体金属层。 该方法还包括执行至少一个蚀刻工艺以至少凹陷导电蚀刻停止层。

公开(公告)号：US20150318398A1

公开(公告)日：2015-11-05

申请号：US14267216

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Min Gyu Sung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, wherein a first portion of the gate structure is positioned above the active region and second portions of the gate structure are positioned above an isolation region formed in the substrate, forming a sidewall spacer adjacent opposite sides of the first portion of the gate structure so as to define first and second continuous epi formation trenches comprised of the spacer that extend for less than the axial length of the gate structure, and forming an epi semiconductor material on the active region within each of the first and second continuous epi formation trenches.

Abstract translation: 所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，其中栅极结构的第一部分位于有源区上方，栅极结构的第二部分位于形成的隔离区的上方 在所述衬底中，形成邻近所述栅极结构的第一部分的相对侧面的侧壁间隔物，以便限定由所述间隔物组成的第一和第二连续外延形成沟槽，所述沟槽延伸小于所述栅极结构的轴向长度，并形成 在第一和第二连续外延形成沟槽的每一个内的有源区域上的外延半导体材料。

公开(公告)号：US08969207B2

公开(公告)日：2015-03-03

申请号：US13798690

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerard M. Schmid ,  Jeremy A. Wahl ,  Richard A. Farrell ,  Chanro Park

IPC: H01L21/311 ,  H01L23/48 ,  H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.

Abstract translation: 本文公开的一种说明性方法包括形成由结构上方的多个离散开口组成的图案化的硬掩模层，其中所述图案化的硬掩模层由多个相交的线型特征组成，在图案化硬的上方形成图案化的蚀刻掩模 掩模层，其暴露多个离散开口中的至少一个但不是全部，并且通过图案化的蚀刻掩模和图案化的硬掩模层中的至少一个暴露的开口进行至少一个蚀刻工艺，以在 结构体。

公开(公告)号：US20150001642A1

公开(公告)日：2015-01-01

申请号：US14476073

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hoon Kim ,  Kisik Choi ,  Chanro Park

IPC: H01L29/49 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.

Abstract translation: 公开了一种改进的场效应晶体管及其制造方法。 在栅腔的基底和侧壁中形成阻挡层堆叠。 阻挡层堆叠具有第一金属层和第二金属层。 栅极电极金属沉积在空腔中。 阻挡层堆叠在栅极腔的侧壁上变薄或去除，以更精确地控制场效应晶体管的电压阈值。

公开(公告)号：US20140273473A1

公开(公告)日：2014-09-18

申请号：US13798690

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gerard M. Schmid ,  Jeremy A. Wahl ,  Richard A. Farrell ,  Chanro Park

IPC: H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

Abstract: One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.

Abstract translation: 本文公开的一种说明性方法包括形成由结构上方的多个离散开口组成的图案化的硬掩模层，其中所述图案化的硬掩模层由多个相交的线型特征组成，在图案化硬的上方形成图案化的蚀刻掩模 掩模层，其暴露多个离散开口中的至少一个但不是全部，并且通过图案化的蚀刻掩模和图案化的硬掩模层中的至少一个暴露的开口进行至少一个蚀刻工艺，以在 结构体。