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    NAND memory arrays
    61.
    发明申请
    NAND memory arrays 审中-公开
    NAND存储器阵列

    公开(公告)号：US20060258093A1

    公开(公告)日：2006-11-16

    申请号：US11486596

    申请日：2006-07-14

    申请人： Michael Violette ,  Garo Derderian ,  Todd Abbott

    发明人： Michael Violette ,  Garo Derderian ,  Todd Abbott

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11526 ,  H01L27/11529 ,  Y10S438/981

    摘要： A NAND memory array has a first dielectric layer formed on a first portion of a semiconductor substrate and a second dielectric layer formed on a second portion of the semiconductor substrate and adjoining the first dielectric layer. The first dielectric layer is thicker than the second dielectric layer. A first gate stack is formed on the first dielectric layer to form a drain select gate. A string of second gate stacks is formed on the second dielectric layer to form a NAND string of floating-gate memory cells. A first end of the NAND string is coupled in series with the drain select gate. A third gate stack is formed on the second dielectric layer to form a source select gate. A second end of the NAND string is coupled in series with the source select gate.

    摘要翻译： NAND存储器阵列具有形成在半导体衬底的第一部分上的第一电介质层和形成在半导体衬底的第二部分上且与第一电介质层相邻的第二电介质层。 第一电介质层比第二电介质层厚。 在第一电介质层上形成第一栅极叠层以形成漏极选择栅极。 在第二电介质层上形成一串第二栅极叠层，以形成浮栅存储器单元的NAND串。 NAND串的第一端与漏极选择栅极串联耦合。 在第二电介质层上形成第三栅极叠层以形成源选择栅极。 NAND串的第二端与源极选择栅极串联耦合。

    Methods of forming capacitors
    62.
    发明申请
    Methods of forming capacitors 失效

    公开(公告)号：US20060258085A1

    公开(公告)日：2006-11-16

    申请号：US11490706

    申请日：2006-07-21

    申请人： Garo Derderian ,  Kevin Shea

    发明人： Garo Derderian ,  Kevin Shea

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/02178 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/31616 ,  H01L28/40 ,  H01L28/56

    摘要： This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first capacitor electrode material is exposed to a nitrogen comprising atmosphere effective to form a dielectric silicon and nitrogen comprising material on the first capacitor electrode material. The dielectric silicon and nitrogen comprising material is exposed to an aqueous fluid comprising a base and an oxidizer. The aqueous fluid has a pH greater than 7.0. After the exposing to the aqueous fluid, an aluminum oxide comprising capacitor dielectric material is deposited over the first capacitor electrode material. A second capacitor electrode material is formed over the aluminum oxide comprising capacitor dielectric material. Other aspects and implementations are contemplated.

    Methods of forming materials
    63.
    发明申请
    Methods of forming materials 有权
    材料成型方法

    公开(公告)号：US20060216933A1

    公开(公告)日：2006-09-28

    申请号：US11413431

    申请日：2006-04-28

    申请人： Demetrius Sarigiannis ,  Garo Derderian ,  Cem Basceri

    发明人： Demetrius Sarigiannis ,  Garo Derderian ,  Cem Basceri

    IPC分类号： H01L21/44

    CPC分类号： C23C18/1283 ,  C23C18/1208 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/125 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/283 ,  H01L21/28556 ,  H01L21/31 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/318

    摘要： The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the chamber. The mixture comprises a precursor of a desired material within a supercritical fluid. The precursor is relatively reactive under one set of conditions and is relatively non-reactive under another set of conditions. The precursor and supercritical fluid mixture is initially provided in the chamber under the conditions at which the precursor is relatively non-reactive. Subsequently, and while maintaining the supercritical state of the supercritical fluid, the conditions within the reaction chamber are changed to the conditions under which the precursor is relatively reactive. The precursor reacts to form the desired material, and at least some of the desired material forms a film on the substrate.

    摘要翻译： 本发明包括在基底上形成膜的方法。 在反应室内设置基板，并且还在室内设置混合物。 该混合物包含超临界流体中期望材料的前体。 前体在一组条件下是相对反应的，并且在另一组条件下相对不反应。 初始和超临界流体混合物最初在前体相对不反应的条件下在室中提供。 随后，在保持超临界流体的超临界状态的同时，将反应室内的条件变更为前体相对反应的条件。 前体反应形成所需的材料，并且所需材料中的至少一些在基材上形成膜。

    Atomic layer deposition methods
    65.
    发明申请
    Atomic layer deposition methods 有权
    原子层沉积法

    公开(公告)号：US20060205228A1

    公开(公告)日：2006-09-14

    申请号：US11414407

    申请日：2006-04-28

    申请人： Demetrius Sarigiannis ,  Garo Derderian ,  Cem Basceri ,  Gurtej Sandhu ,  F. Gealy ,  Chris Carlson

    发明人： Demetrius Sarigiannis ,  Garo Derderian ,  Cem Basceri ,  Gurtej Sandhu ,  F. Gealy ,  Chris Carlson

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/32051 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/45531 ,  C23C16/45534 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/31616

    摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.

    摘要翻译： 本发明包括在基板上形成沉积的组合物层的原子层沉积方法。 该方法包括将半导体衬底定位在原子层沉积室内。 在基材上形成中间组合物单层，随后是与中间体组合物反应所需的沉积组合物，统称为将多种不同的组合物沉积前体流到沉积室内的基底。 材料粘附到室内部件表面，从而依次形成。 在这种顺序形成之后，反应性气体流入到与多种不同的沉积前体不同的组合物中，并有效地与这种粘附材料反应。 在反应气体流动之后，重复这种顺序形成。 考虑进一步的实现。

    Methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and methods of forming trench isolation in the fabrication of integrated circuitry
    67.
    发明申请
    Methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and methods of forming trench isolation in the fabrication of integrated circuitry 失效
    在制造集成电路中沉积含二氧化硅的层的方法以及在集成电路的制造中形成沟槽隔离的方法

    公开(公告)号：US20060189159A1

    公开(公告)日：2006-08-24

    申请号：US11404703

    申请日：2006-04-14

    申请人： Garo Derderian ,  Chris Hill

    发明人： Garo Derderian ,  Chris Hill

    IPC分类号： H01L21/31

    CPC分类号： H01L21/02164 ,  C23C16/0272 ,  C23C16/402 ,  H01L21/02145 ,  H01L21/02214 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76227

    摘要： This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate. At least one halogen is provided within the chamber during at least one of the aluminum containing organic precursor flowing and the alkoxysilanol flowing under conditions effective to reduce rate of the deposit of the silicon dioxide comprising layer over the substrate than would otherwise occur under identical conditions but for providing the halogen. Other implementations are contemplated.

    摘要翻译： 本发明包括在制造集成电路中沉积含二氧化硅的层的方法以及在集成电路的制造中形成沟槽隔离的方法。 在一个实施方案中，在集成电路的制造中沉积含二氧化硅的层的方法包括将含有铝的有机前体流动到含有半导体衬底的室，该半导体衬底有效地在衬底上沉积含铝层。 烷氧基硅烷流到包含室内的包含铝的基材的基材中，有效地将二氧化硅包含层沉积在基材上。 在含铝的有机前驱体和烷氧基硅烷中的至少一种中，至少有一个卤素在有效地降低衬底上沉积二氧化硅层的条件下流动的条件下流动，这与在相同条件下将会发生的情况相反，但是 用于提供卤素。 考虑其他实现。

    NAND memory arrays and methods
    69.
    发明申请
    NAND memory arrays and methods 有权
    NAND存储器阵列和方法

    公开(公告)号：US20060040447A1

    公开(公告)日：2006-02-23

    申请号：US10920561

    申请日：2004-08-18

    申请人： Michael Violette ,  Garo Derderian ,  Todd Abbott

    发明人： Michael Violette ,  Garo Derderian ,  Todd Abbott

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11526 ,  H01L27/11529 ,  Y10S438/981

    摘要： NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND memory array. The first dielectric layer and the plurality of first gate stacks formed thereon form a NAND string of memory cells of the memory array. A second gate stack is formed on a second dielectric layer that is formed on the substrate adjacent the first dielectric layer. The second dielectric layer with the second gate stack formed thereon forms a drain select gate adjacent an end of the NAND string. The second dielectric layer is thicker than the first dielectric layer.

    摘要翻译： 提供NAND存储器阵列和方法。 在形成在NAND存储器阵列的衬底上的第一电介质层上形成多个第一栅极叠层。 形成在其上的第一介电层和多个第一栅极堆叠形成存储器阵列的存储器单元的NAND串。 在与第一介电层相邻的基板上形成的第二电介质层上形成第二栅极叠层。 其上形成有第二栅极堆叠的第二介电层形成与NAND串的端部相邻的漏极选择栅极。 第二电介质层比第一电介质层厚。

    Semiconductor substrate
    70.
    发明申请
    Semiconductor substrate 有权
    半导体衬底

    公开(公告)号：US20060027836A1

    公开(公告)日：2006-02-09

    申请号：US11241488

    申请日：2005-09-29

    申请人： Garo Derderian ,  Cem Basceri

    发明人： Garo Derderian ,  Cem Basceri

    IPC分类号： H01L27/148

    CPC分类号： C23C16/0227 ,  C23C16/0254 ,  C23C16/0272 ,  C23C16/0281 ,  C23C16/14 ,  C23C16/42 ,  C23C16/56 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855

    摘要： The invention includes methods of forming conductive metal suicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a crystalline form TiN, WN, elemental form W, or SiC comprising layer is deposited onto the exposed elemental silicon containing surface to a thickness no greater than 50 Angstroms. Such layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal rich silicide is deposited onto the plasma exposed layer. At least one of metal of the conductive reaction layer or elemental silicon of the substrate is diffused along columnar grain boundaries of the crystalline form layer effective to cause a reaction of metal of the conductive reaction layer with elemental silicon of the substrate to form a conductive metal silicide comprising contact region electrically connecting the conductive reaction layer with the substrate. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括通过金属与硅的反应形成导电金属硅化物的方法。 在一个实施方案中，这种方法包括提供包括暴露的含元素硅的表面的半导体衬底。 将结晶形态TiN，WN，元素形式W或包含SiC的层中的至少一种沉积到暴露的含元素硅表面上至不大于50埃的厚度。 这种层暴露于等离子体，并且包含元素金属或富金属硅化物中的至少一种的导电反应层沉积到等离子体暴露层上。 基板的导电性反应层或元素硅的金属中的至少一种沿结晶层的柱状晶界扩散，有效地引起导电性反应层的金属与基板的元素硅的反应，形成导电性金属 硅化物，其包括将导电反应层与基底电连接的接触区域。 考虑了其他方面和实现。