Method and apparatus for detecting the endpoint in chemical-mechanical
polishing of semiconductor wafers
    61.
    发明授权
    Method and apparatus for detecting the endpoint in chemical-mechanical polishing of semiconductor wafers 失效
    用于检测半导体晶片的化学机械抛光中的端点的方法和装置

    公开(公告)号:US5663797A

    公开(公告)日:1997-09-02

    申请号:US650087

    申请日:1996-05-16

    摘要: A method and apparatus for detecting the endpoint of CMP processing on semiconductor wafer in which a lower layer of material with a first reflectivity is positioned under an upper layer of material with a second reflectivity. Initially an endpoint site is selected on the wafer in a critical area where a boundary between the upper and lower layers defines the desired endpoint of the CMP process. The critical area on the wafer is generally determined by analyzing in the circuit design and the polishing characteristics of previously polished test wafers to denote the last points on the wafer from which the upper layer is desirably removed by CMP processing. After an endpoint site is selected, a light beam impinges the polished surface of the wafer and reflects off of the surface of the wafer to a photo-sensor. The photosensor senses the actual intensity of the reflected light beam. The actual intensity of the reflected light beam is compared with an expected intensity to determine whether the upper layer has been adequately removed from the endpoint site. The actual intensity is preferably compared with an expected intensity for light reflected from one of the upper or lower layers, and the endpoint is preferably detected when the actual intensity of the reflected light beam is either substantially the same as the expected intensity for light reflected from the lower layer or substantially different from the expected intensity for light reflected from the upper layer.

    摘要翻译: 一种用于检测半导体晶片上的CMP处理的终点的方法和装置,其中具有第一反射率的下层材料位于具有第二反射率的上层材料的下方。 最初,在晶圆上选择端点位置,其中上层和下层之间的边界限定CMP工艺的期望端点。 晶片上的关键区域通常通过在电路设计中分析和先前抛光的测试晶片的抛光特性来确定,以表示通过CMP处理希望从其上去除上层的晶片上的最后点。 在选择端点位置之后,光束照射晶片的抛光表面并从晶片的表面反射到光电传感器。 光传感器感测反射光束的实际强度。 将反射光束的实际强度与预期强度进行比较,以确定上层是否已经从端点位点被适当地去除。 优选地将实际强度与从上层或下层中的一层反射的光的预期强度进行比较,并且优选地,当反射光束的实际强度基本上与从 下层或与从上层反射的光的预期强度基本上不同。

    RESONATOR FOR THERMO OPTIC DEVICE
    62.
    发明申请
    RESONATOR FOR THERMO OPTIC DEVICE 有权
    热电偶装置谐振器

    公开(公告)号:US20120237165A1

    公开(公告)日:2012-09-20

    申请号:US13483542

    申请日:2012-05-30

    IPC分类号: G02B6/26

    摘要: A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is formed on a surface of the lower cladding. Since upper surfaces of the resonator and waveguide are substantially coplanar, the aspect ratio, as between the waveguide and resonator in an area where the waveguide and resonator front one another, decreases thereby increasing the bandwidth of the resonator. The depression is formed by photomasking and etching the lower cladding before forming the resonator and waveguide. Pluralities of resonators are also taught that are formed in a plurality of depressions of the lower cladding. To decrease resonator bandwidth, waveguide(s) are formed in the depression(s) of the lower cladding while the resonator is formed on the surface. Thermo optic devices formed with these resonators are also taught.

    摘要翻译: 用于热光器件的谐振器以与波导相同的工艺步骤形成,并且形成在下包层的凹陷中,同时波导形成在下包层的表面上。 由于谐振器和波导的上表面基本上是共面的,因此在波导和谐振器彼此前向的区域中的波导和谐振器之间的纵横比减小,从而增加了谐振器的带宽。 在形成谐振器和波导之前,通过光掩模和蚀刻下部包层形成凹陷。 还教导了形成在下部包层的多个凹部中的多个谐振器。 为了减小谐振器带宽,当在表面上形成谐振器时,在下包层的凹陷中形成波导。 还教导了用这些谐振器形成的热光器件。

    ENHANCED ATOMIC LAYER DEPOSITION
    65.
    发明申请
    ENHANCED ATOMIC LAYER DEPOSITION 有权
    增强原子层沉积

    公开(公告)号:US20080251828A1

    公开(公告)日:2008-10-16

    申请号:US11856571

    申请日:2007-09-17

    摘要: A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF5 and NH3. In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.

    摘要翻译: 描述了增加原子层沉积的方法。 在一个实施例中,增强是使用等离子体。 等离子体在将第二前体流入室之前开始。 第二前体与先前的前体反应以在基底上沉积一层。 在一个实施方案中,该层包括来自第一和第二前体中的每一个的至少一种元素。 在一个实施例中,层是TaN。 在一个实施方案中,前体是TaF 5 N和NH 3。 在一个实施方案中,等离子体在第一前体的脉冲与第二前体的脉冲之间的吹扫气流期间开始。 在一个实施例中,增强是热能。 在一个实施例中,热能大于ALD(> 300摄氏度)通常接受的热能。 该增强有助于前体在基底上沉积一层的反应。

    Method of forming a coupling dielectric Ta2O5 in a memory device
    66.
    发明授权
    Method of forming a coupling dielectric Ta2O5 in a memory device 有权
    在存储器件中形成耦合电介质Ta 2 O 5的方法

    公开(公告)号:US07241661B2

    公开(公告)日:2007-07-10

    申请号:US10716765

    申请日:2003-11-19

    IPC分类号: H01L21/8242

    摘要: A method of forming a coupling dielectric in a memory cell includes forming an oxide on a substrate, forming Ta2O5 on the oxide, oxidizing the Ta2O5 with rapid thermal process (RTP) at a temperature above the crystallization temperature for Ta2O5, forming a cell nitride on the oxidized Ta2O5, and forming a wetgate oxide on the cell nitride.

    摘要翻译: 在存储单元中形成耦合电介质的方法包括在衬底上形成氧化物,在氧化物上形成Ta 2 O 5 O 3,氧化Ta 2 O 3, 在高于Ta 2 O 5 O 5的结晶温度的温度下用快速热处理(RTP)处理,形成细胞氮化物 在氧化的Ta 2 O 5 O上,并在电池氮化物上形成湿式氧化物。

    Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3
    67.
    发明授权
    Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3 有权
    使用N2O和O3的混合物在含硅表面上生长电介质层的方法

    公开(公告)号:US07235498B2

    公开(公告)日:2007-06-26

    申请号:US11075187

    申请日:2005-03-08

    摘要: This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting. The presence of O3 in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.

    摘要翻译: 本发明体现在用于通过使其经受一氧化二氮(N 2 O 2 O)和臭氧(O 3 O 3)的气体混合物在硅上生长高质量二氧化硅层的改进方法, SUB>)。 氧化气氛中O 3 3的存在与其中N 2 O 2是唯一的氧化剂的环境相比,大大地提高了氧化速率。 除了提高硅的氧化速率之外,假设O 3 3的存在妨碍了二氧化硅层和未反应的硅表面界面附近的薄氧氮化硅层的生长,其中 在N 2 O 2存在下进行氧化,实际上是自限制的。 氧化气氛中的O 3 3的存在不会损害氧化物的可靠性,如在强的氟化物存在下用N 2 O 2氧化硅的情况, 含有氧化剂如NF 3或SF 6。

    Semiconductor manufacturing system for forming metallization layer
    68.
    发明授权
    Semiconductor manufacturing system for forming metallization layer 有权
    用于形成金属化层的半导体制造系统

    公开(公告)号:US07189317B2

    公开(公告)日:2007-03-13

    申请号:US10217618

    申请日:2002-08-13

    IPC分类号: C25D5/00

    摘要: A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. A second layer is formed outwardly from the first layer. Portions of the second layer are selectively removed such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias. The first and second layers are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer. Further, metal ions deposited on the first layer during a positive duty cycle are removed from the first layer during a negative duty cycle. Finally, exposed portions of the first layer are selectively removed.

    摘要翻译: 一种形成金属化层的方法。 第一层从半导体衬底向外形成。 通过第一层到半导体衬底形成接触通孔。 第二层从第一层向外形成。 选择性地去除第二层的部分,使得第二层的剩余部分限定了金属化层和接触孔的布局。 通过将具有正占空比和负占空比的双极调制电压施加到含有金属离子的溶液中的层来电镀第一层和第二层。 选择电压和表面电位使得金属离子沉积在第二层的剩余部分上。 此外,在负占空比期间,在正占空比期间沉积在第一层上的金属离子在第一层中被去除。 最后,选择性地去除第一层的暴露部分。

    Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3
    69.
    发明授权
    Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3 失效
    使用N2O和O3的混合物在含硅表面上生长电介质层的方法

    公开(公告)号:US06864125B2

    公开(公告)日:2005-03-08

    申请号:US10642705

    申请日:2003-08-18

    摘要: This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting. The presence of O3 in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.

    摘要翻译: 本发明体现在通过使其经受一氧化二氮(N 2 O)和臭氧(O 3)的气体混合物在硅上生长高品质二氧化硅层的改进方法。 氧化气氛中O3的存在与其中N2O是唯一氧化剂的氛围相比,大大提高了氧化速率。 除了提高硅的氧化速率之外,假设O3的存在干扰了在二氧化硅层和未反应的硅表面的界面附近生长的薄氧氮化硅层,这在单独的N2O存在下进行氧化 实际上是自限制的。 氧化气氛中O 3的存在不会损害氧化物的可靠性,如在含氟的氧化剂如NF3或SF6的存在下用N 2 O氧化硅的情况。

    Small grain size, conformal aluminum interconnects and method for their formation
    70.
    发明申请
    Small grain size, conformal aluminum interconnects and method for their formation 有权
    小晶粒尺寸,共形铝互连及其形成方法

    公开(公告)号:US20050006774A1

    公开(公告)日:2005-01-13

    申请号:US10899736

    申请日:2004-07-27

    摘要: A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientation. Finally, an aluminum film is formed on the second layer of titanium nitride. Optionally, a titanium silicide layer is formed on the semiconductor structure prior to the step of forming the first layer of titanium nitride. Interconnects formed according to the invention have polycrystalline aluminum films with grain sizes of approximately less than 0.25 microns.

    摘要翻译: 第一层氮化钛(TiN)形成在诸如互连通孔的半导体结构上。 然后,在第一TiN层上形成第二TiN层。 第一层TiN是无定形的。 第二层TiN是多晶的,具有混晶粒取向。 最后,在第二层氮化钛上形成铝膜。 可选地,在形成第一层氮化钛的步骤之前,在半导体结构上形成硅化钛层。 根据本发明形成的互连件具有晶粒尺寸大约小于0.25微米的多晶铝膜。