公开(公告)号：US20230309320A1

公开(公告)日：2023-09-28

申请号：US17656045

申请日：2022-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Chen Zhang

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/08 ,  H01L43/14 ,  H01L43/04

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1697 ,  H01L43/08 ,  H01L43/14 ,  H01L43/04

Abstract: Embodiments are disclosed for a system. The system includes a semiconductor structure. The semiconductor structure includes a wafer, multiple transistors, and a magnetoresistive random access memory (MRAM) cell disposed on the backside of the wafer. The transistors are disposed on a front end of line (FEOL) of the wafer. The MRAM cell is connected to a source-drain of the transistors by a contact disposed on the backside of the wafer. The transistors are in direct electrical contact with the MRAM cell by at least one contact.

公开(公告)号：US20230299176A1

公开(公告)日：2023-09-21

申请号：US18324240

申请日：2023-05-26

Applicant: International Business Machines Corporation

Inventor： Lan Yu ,  Kangguo Cheng ,  Heng Wu ,  Chen Zhang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/42392

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.

公开(公告)号：US11729996B2

公开(公告)日：2023-08-15

申请号：US17444174

申请日：2021-07-30

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Ruilong Xie ,  Julien Frougier ,  Bruce B. Doris

IPC: G11C16/04 ,  H10B61/00 ,  H10N50/80 ,  H10N50/01 ,  G11C11/16

CPC classification number: H10B61/00 ,  G11C11/161 ,  G11C11/1675 ,  H10N50/01 ,  H10N50/80

Abstract: An embedded eMRAM device for eFlash replacement including an MTJ pillar located between a top electrode and a bottom electrode for forming an MRAM array. The bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, while the top electrode is disposed above the MTJ pillar and surrounded by a second dielectric spacer. A bottom metal plate is disposed on opposing sides of the bottom electrode between first and second dielectric layers and is electrically separated from the bottom electrode by the first dielectric spacer. A top metal plate is disposed on opposing sides of the top electrode between third and fourth dielectric layers and is electrically separated from the top electrode by the second dielectric spacer. A bias voltage applied to the top metal plate and the bottom metal plate generates an external electric field on the MTJ pillar for creating a VCMA effect.

公开(公告)号：US20230238285A1

公开(公告)日：2023-07-27

申请号：US17648817

申请日：2022-01-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Junli Wang ,  Teresa J. Wu ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L21/02 ,  H01L23/50 ,  H01L25/065 ,  H01L27/11551

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/823871 ,  H01L23/50 ,  H01L25/0652 ,  H01L27/11551 ,  H01L27/11597

Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.

公开(公告)号：US11688635B2

公开(公告)日：2023-06-27

申请号：US17131998

申请日：2020-12-23

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Junli Wang ,  Ruqiang Bao

IPC: H01L23/532 ,  H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/76889 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/535 ,  H01L23/53266 ,  H01L27/0924 ,  H01L29/6653

Abstract: Embodiments of the invention are directed to an integrated circuit. A non-limiting example of the integrated circuit includes a transistor formed over a substrate. A dielectric region is formed over the transistor and the substrate. A trench is positioned in the dielectric region and over a S/D region of the transistor. A first liner and a conductive plug are within the trench such that the first liner and the conductive plug are only present within a bottom portion of the trench. A substantially oxygen-free replacement liner and a S/D contact are within the top portion of the trench such that a bottom contact surface of the S/D contact directly couples to a top surface of the conductive plug.

公开(公告)号：US20230197607A1

公开(公告)日：2023-06-22

申请号：US17554799

申请日：2021-12-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Heng Wu ,  Julien Frougier ,  Min Gyu Sung

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/5226

Abstract: Semiconductor devices and methods of forming the same include forming a multilayer dielectric structure, including a first dielectric layer and a second dielectric layer, between dielectric lines. Exposed portions of the first dielectric layer are etched away, leaving remnants between the second dielectric layer and the dielectric lines, to decrease a width of the multilayer dielectric structure. Conductive lines are formed between the dielectric lines, on respective sides of the multilayer dielectric structure.

公开(公告)号：US20230187443A1

公开(公告)日：2023-06-15

申请号：US17548913

申请日：2021-12-13

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Chen Zhang ,  Heng Wu ,  Julien Frougier ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66742

Abstract: A FET channel comprises a stack of silicon nanosheets. The silicon nanosheets are oriented parallel to a planar portion of the FET in which the FET channel is formed. The FET channel also comprises a vertical blocker fin. The vertical blocker fin is attached to at least one nanosheet in the stack of nanosheets.

公开(公告)号：US20230101235A1

公开(公告)日：2023-03-30

申请号：US17486911

申请日：2021-09-28

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Ardasheir Rahman ,  HEMANTH JAGANNATHAN ,  Robert ROBISON ,  Brent Anderson ,  Heng Wu

IPC: H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/76 ,  H01L29/08

Abstract: A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

公开(公告)号：US20230031589A1

公开(公告)日：2023-02-02

申请号：US17444174

申请日：2021-07-30

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Ruilong Xie ,  Julien Frougier ,  Bruce B. Doris

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C11/16

Abstract: An embedded eMRAM device for eFlash replacement including an MTJ pillar located between a top electrode and a bottom electrode for forming an MRAM array. The bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, while the top electrode is disposed above the MTJ pillar and surrounded by a second dielectric spacer. A bottom metal plate is disposed on opposing sides of the bottom electrode between first and second dielectric layers and is electrically separated from the bottom electrode by the first dielectric spacer. A top metal plate is disposed on opposing sides of the top electrode between third and fourth dielectric layers and is electrically separated from the top electrode by the second dielectric spacer. A bias voltage applied to the top metal plate and the bottom metal plate generates an external electric field on the MTJ pillar for creating a VCMA effect.

公开(公告)号：US20230031478A1

公开(公告)日：2023-02-02

申请号：US17444176

申请日：2021-07-30

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dimitri Houssameddine ,  Saba Zare ,  Karthik Yogendra

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A memory device with in-array magnetic shield includes an electrically conductive structure embedded within an interconnect dielectric material located above a first metal layer. The electrically conductive structure includes a bottom electrode. The memory device further includes a magnetic tunnel junction stack located above the bottom electrode, a dielectric filling layer surrounding the magnetic tunnel junction stack, one or more connecting vias extending through the dielectric filling layer and the interconnect dielectric material until a top portion of the first metal layer, and one or more dummy vias located between the one or more connecting vias and the magnetic tunnel junction stack for conducting an external magnetic field around the memory device.