公开(公告)号：US10157838B2

公开(公告)日：2018-12-18

申请号：US15824916

申请日：2017-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L21/762 ,  H01L21/683 ,  H01L23/522 ,  H01L27/12 ,  H01L29/06 ,  H01L23/485

Abstract: A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, includes forming a trench in the device layer. The trench is filled with a contact plug. The backside device contact includes the contact plug. After the trench is filled with the contact plug, the handle wafer is removed to reveal the buried insulator layer. The buried insulator layer is partially removed to expose the trench containing the contact plug. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate. A device structure is formed using the device layer.

公开(公告)号：US20180286748A1

公开(公告)日：2018-10-04

申请号：US15994965

申请日：2018-05-31

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/74 ,  H01L21/762 ,  H01L29/10 ,  H01L29/06 ,  H01L27/12 ,  H01L21/683 ,  H01L23/482

Abstract: A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer. An electrically-conducting connection is located in a first trench extending from the device layer through the buried insulator layer to a trap-rich layer such that the electrically-conducting connection is coupled with a substrate.

公开(公告)号：US20180090434A1

公开(公告)日：2018-03-29

申请号：US15824921

申请日：2017-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L23/528 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L21/768 ,  H01L21/683 ,  H01L23/522 ,  H01L23/485

CPC classification number: H01L23/528 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/1203 ,  H01L29/0649 ,  H01L2221/68327 ,  H01L2221/68372

Abstract: A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, includes forming a trench in the device layer. A trench is formed in the device layer. A sacrificial plug is formed in the trench. The handle wafer is removed to reveal the buried insulator layer. The buried insulator layer is partially removed to expose the sacrificial plug at a bottom of the trench. The sacrificial plug is removed. Backside processing of the buried insulator layer is performed. The trench is filled with a conductor to form a contact plug. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate.

公开(公告)号：US20180090433A1

公开(公告)日：2018-03-29

申请号：US15824916

申请日：2017-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L23/528 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L21/768 ,  H01L21/683 ,  H01L23/522 ,  H01L23/485

CPC classification number: H01L23/528 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/1203 ,  H01L29/0649 ,  H01L2221/68327 ,  H01L2221/68372

Abstract: A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, includes forming a trench in the device layer. The trench is filled with a contact plug. The backside device contact includes the contact plug. After the trench is filled with the contact plug, the handle wafer is removed to reveal the buried insulator layer. The buried insulator layer is partially removed to expose the trench containing the contact plug. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate. A device structure is formed using the device layer.

公开(公告)号：US09843303B2

公开(公告)日：2017-12-12

申请号：US14755522

申请日：2015-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H01L41/047 ,  H03H9/25 ,  H03H9/13 ,  H03H9/64 ,  H01L41/08 ,  G06F17/50 ,  H03H3/08 ,  H03H3/007 ,  H03H9/02

CPC classification number: H03H9/13 ,  G06F17/5081 ,  H01L41/08 ,  H03H3/08 ,  H03H9/02543 ,  H03H9/64 ,  H03H9/6403 ,  H03H9/6413 ,  H03H2003/0071 ,  H03H2009/02299 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a fixed electrode with a plurality of fingers on the piezoelectric substrate. The method further includes forming a moveable electrode with a plurality of fingers over the piezoelectric substrate. The method further includes forming actuators aligned with one or more of the plurality of fingers of the moveable electrode.

公开(公告)号：US09627575B2

公开(公告)日：2017-04-18

申请号：US14483584

申请日：2014-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson

IPC: H01L31/0232 ,  H01L21/00 ,  H01L31/18 ,  H01L31/103 ,  G02B6/12 ,  H01L31/028 ,  H01P1/17 ,  H01L31/02 ,  H01P3/16

CPC classification number: H01L31/1872 ,  G02B6/12 ,  G02B6/12004 ,  H01L31/02005 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/103 ,  H01L31/1808 ,  H01L31/1864 ,  H01L2223/6627 ,  H01P1/172 ,  H01P3/16 ,  Y02E10/50

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

公开(公告)号：US20170012055A1

公开(公告)日：2017-01-12

申请号：US15274423

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/532 ,  H01L29/10

CPC classification number: H01L21/76895 ,  H01L21/6835 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/4825 ,  H01L23/4827 ,  H01L23/53271 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1087 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368

Abstract: A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed using a device layer of the silicon-on-insulator substrate. A trap-rich layer is between a substrate and a buried insulator layer of the silicon on-insulator substrate. An electrically-conducting connection is located in a trench extending from the device layer through the buried insulator layer to the trap-rich layer such that the electrically-conducting connection is coupled with the substrate. The electrically-conducting connection at least partially comprised of trap-rich material.

Abstract translation: 使用绝缘体上硅衬底形成器件结构。 器件结构包括使用绝缘体上硅衬底的器件层形成的第一开关和第二开关。 陷阱丰富的层位于衬底和绝缘体上硅衬底的掩埋绝缘体层之间。 导电连接位于从器件层通过掩埋绝缘体层延伸到富集陷阱的沟槽中，使得导电连接与衬底耦合。 至少部分地由富含阱的材料构成的导电连接。

公开(公告)号：US20160372372A1

公开(公告)日：2016-12-22

申请号：US14744681

申请日：2015-06-19

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L23/482 ,  H01L23/48

CPC classification number: H01L21/76895 ,  H01L21/6835 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/76898 ,  H01L23/4825 ,  H01L23/4827 ,  H01L23/53271 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1087 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368

Abstract: Device structures and fabrication methods for a backside contact to a final substrate An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.

Abstract translation: 用于与最终衬底的背面接触的器件结构和制造方法形成延伸穿过绝缘体上硅衬底的器件层并且部分地穿过绝缘体上硅衬底的掩埋绝缘体层的导电连接。 在形成导电连接之后，去除绝缘体上硅衬底的处理晶片。 在移除手柄晶片之后，部分去除掩埋绝缘体层以露出导电连接。 在埋入绝缘体层被部分去除之后，最后的衬底被耦合到埋入绝缘体层，使得导电连接与最终衬底耦合。

公开(公告)号：US09214561B2

公开(公告)日：2015-12-15

申请号：US13929256

申请日：2013-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michel J. Abou-Khalil ,  Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph ,  James A. Slinkman

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/786 ,  H01L21/28 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L29/78654 ,  H01L21/28123 ,  H01L21/84 ,  H01L29/66613

Abstract: An integrated recessed thin body field effect transistor (FET) and methods of manufacture are disclosed. The method includes recessing a portion of a semiconductor material. The method further includes forming at least one gate structure within the recessed portion of the semiconductor material.

Abstract translation: 公开了集成的凹陷薄体场效应晶体管（FET）及其制造方法。 该方法包括使半导体材料的一部分凹陷。 该方法还包括在半导体材料的凹陷部分内形成至少一个栅极结构。

公开(公告)号：US08987067B2

公开(公告)日：2015-03-24

申请号：US13782537

申请日：2013-03-01

Applicant: International Business Machines Corporation

Inventor： Robert L. Barry ,  Phillip F. Chapman ,  Jeffrey P. Gambino ,  Michael L. Gautsch ,  Mark D. Jaffe ,  Kevin N. Ogg ,  Bradley A. Orner

IPC: H01L21/332 ,  H01L21/762 ,  H01L23/31

CPC classification number: H01L21/76267 ,  G06F17/5045 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/562 ,  H01L23/585 ,  H01L23/66 ,  H01L29/0619 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure.

Abstract translation: 公开了一种在衬底中具有电绝缘间隙的保护环结构，以减少或消除集成电路芯片的器件耦合，制造方法和设计结构。 该方法包括在电介质层内形成包括多个金属层的保护环结构。 该方法还包括形成扩散区域以使由保护环结构的分段部分形成的衬底中的间隙电绝缘。