公开(公告)号：US10109553B2

公开(公告)日：2018-10-23

申请号：US15471090

申请日：2017-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Max L. Lifson ,  James A. Slinkman ,  Theodore G. Van Kessel ,  Randy L. Wolf

IPC: H01L29/08 ,  H01L23/367 ,  H01L29/06 ,  H01L29/732 ,  H01L29/41 ,  H01L29/45

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

公开(公告)号：US10068827B2

公开(公告)日：2018-09-04

申请号：US15401660

申请日：2017-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Max L. Lifson ,  James A. Slinkman ,  Theodore G. Van Kessel ,  Randy L. Wolf

IPC: H01L29/08 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/02 ,  H01L29/41

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

公开(公告)号：US09847415B2

公开(公告)日：2017-12-19

申请号：US14523076

申请日：2014-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7834 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/423 ,  H01L29/66575

Abstract: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

公开(公告)号：US09666701B2

公开(公告)日：2017-05-30

申请号：US15074165

申请日：2016-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Max L. Lifson ,  James A. Slinkman ,  Theodore G. Van Kessel ,  Randy L. Wolf

IPC: H01L29/08 ,  H01L29/732 ,  H01L23/367 ,  H01L23/373 ,  H01L29/78 ,  H01L29/45 ,  H01L23/525 ,  H01L21/02 ,  H01L21/285 ,  H01L21/762 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/41 ,  H01L21/48 ,  H01L23/48 ,  H01L23/485

CPC classification number: H01L23/3677 ,  B82Y10/00 ,  H01L21/02112 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02271 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/4882 ,  H01L21/7624 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

公开(公告)号：US09257324B2

公开(公告)日：2016-02-09

申请号：US14230206

申请日：2014-03-31

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Robert M. Rassel ,  Mark E. Stidham

IPC: H01L27/04 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/265 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L21/76224 ,  H01L21/26506 ,  H01L21/823892 ,  H01L27/04 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0802 ,  H01L27/0811 ,  H01L27/0928

Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

Abstract translation: 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

公开(公告)号：US09165819B2

公开(公告)日：2015-10-20

申请号：US14546058

申请日：2014-11-18

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Jeffrey E. Hanrahan ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Dale W. Martin ,  Gerd Pfeiffer ,  James A. Slinkman

IPC: H01L21/76 ,  H01L21/04 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324

CPC classification number: H01L21/76251 ,  H01L21/04 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324

Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.

Abstract translation: 根据本文的方法，在第一材料被植入之后，衬底的第一侧被注入第一材料，以将衬底的第一侧的结晶结构从第一结晶状态改变到第二结晶状态。 在植入第一种材料之后，第二种材料沉积在基底的第一面上。 绝缘体层的第一面在衬底的第一侧上与第二材料接合。 在绝缘体层与第二材料结合之后，在绝缘体层的与绝缘体层的第一侧相对的第二侧上形成集成电路器件。 集成电路器件进行热退火。 第一种材料在退火过程中保持衬底的第一面的第二结晶状态。

公开(公告)号：US08963293B2

公开(公告)日：2015-02-24

申请号：US14151582

申请日：2014-01-09

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

IPC: H01L23/58 ,  H01L29/16 ,  H01L21/762

CPC classification number: H01L29/16 ,  H01L21/76254

Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

Abstract translation: 半导体结构及其形成方法。 在一个实施例中，形成绝缘体上硅（SOI）晶片衬底的方法包括：提供处理衬底; 在所述手柄衬底上形成高电阻率材料层，所述高电阻率材料层包括非晶碳化硅（SiC），多晶SiC，无定形金刚石或多晶金刚石中的一种; 在所述高电阻率材料层上形成绝缘体层; 并将施主晶片接合到绝缘体层的顶表面以形成SOI晶片衬底。

公开(公告)号：US08722508B2

公开(公告)日：2014-05-13

申请号：US13832929

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

IPC: H01L21/764

CPC classification number: H01L21/76283 ,  H01L21/76289 ,  H01L27/0738 ,  H01L27/1203 ,  H01L29/0649

Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Abstract translation: 绝缘体上硅（SOI）衬底中的低谐波射频（RF）开关及其制造方法。 一种方法包括通过绝缘体层形成至少一个沟槽。 所述至少一个沟槽与形成在所述绝缘体层上的有源区域中的器件相邻。 该方法还包括在绝缘体层之下的衬底中形成至少一个空腔，并从该至少一个沟槽横向延伸到该器件的下方。

公开(公告)号：US08564067B2

公开(公告)日：2013-10-22

申请号：US13772402

申请日：2013-02-21

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC: H01L21/70

CPC classification number: H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

Abstract translation: 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

公开(公告)号：US10600893B2

公开(公告)日：2020-03-24

申请号：US16009561

申请日：2018-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alan B. Botula ,  Max L. Lifson ,  James A. Slinkman ,  Theodore G. Van Kessel ,  Randy L. Wolf

IPC: H01L29/732 ,  H01L23/373 ,  H01L29/78 ,  H01L29/45 ,  H01L23/525 ,  H01L21/02 ,  H01L21/285 ,  H01L29/10 ,  H01L29/08 ,  H01L49/02 ,  H01L29/06 ,  H01L21/762 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/41 ,  H01L23/367 ,  H01L21/48 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/48 ,  H01L23/485

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.