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公开(公告)号：US11861184B2
公开(公告)日：2024-01-02
申请号：US17943536
申请日：2022-09-13
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel
CPC classification number: G06F3/0622 , G06F3/0655 , G06F3/0673 , G11C29/42
Abstract: A method for determining a resultant data word when accessing memory cells includes reading a set of memory cells, and determining first and second data words therefrom. Each memory cell is assigned a component of the first and second data words. The first and second data words for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller. The first and second data words assume at least one third value if neither condition is satisfied. The resultant data word is determined based on the first or second data words. A corresponding device is also proposed.
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公开(公告)号：US11722153B2
公开(公告)日：2023-08-08
申请号：US17579721
申请日：2022-01-20
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel , Thomas Rabenalt
CPC classification number: H03M13/1575 , H03M13/152
Abstract: Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s1 of an error syndrome and a second partial error syndrome s2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.
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公开(公告)号：US11650877B2
公开(公告)日：2023-05-16
申请号：US16881473
申请日：2020-05-22
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Klaus Oberlaender , Christian Badack , Michael Goessel
CPC classification number: G06F11/1016 , G06F11/1048 , G06F11/3037 , G06F11/34 , H03M13/1174 , H03M13/13 , H03M13/19 , H03M13/618
Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.
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公开(公告)号：US11455104B2
公开(公告)日：2022-09-27
申请号：US17144723
申请日：2021-01-08
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel
Abstract: Method for determining a resultant data word when accessing memory cells of a memory, comprising the steps: (a) reading a set of memory cells, (b) wherein a first data word and a second data word are determined from the read set of memory cells, wherein each memory cell is assigned a component of the first data word and the corresponding component of the second data word, (c) wherein the first data word and the second data word for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller, (d) wherein the first data word and the second data word for the respective memory cell assume at least one third value if the conditions according to feature (c) are not satisfied, and (e) determining the resultant data word on the basis of the first data word or on the basis of the second data word. A corresponding device is also proposed.
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公开(公告)号：US10567007B2
公开(公告)日：2020-02-18
申请号：US15449029
申请日：2017-03-03
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Roland Brachmann , Michael Goessel
Abstract: A method is proposed for processing a data word, in which the data word comprises a first partial data word and a second partial data word, in which first checkbits are defined for the first partial data word, wherein the first partial data word and the first checkbits form a first codeword, in which second checkbits are defined for the second partial data word, wherein the second partial data word and the second checkbits form a second codeword, in which third checkbits are defined for the data word, wherein at least (i) the data word, (ii) a linking of the first checkbits with the second checkbits, and (iii) the third checkbits are parts of a third codeword.
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Patent Agency Ranking
公开(公告)号：US10200065B2
公开(公告)日：2019-02-05
申请号：US13975621
申请日：2013-08-26
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt , Stephane Lacouture
Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
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公开(公告)号：US09805771B2
公开(公告)日：2017-10-31
申请号：US14190435
申请日：2014-02-26
Applicant: Infineon Technologies AG
Inventor： Ulrich Loibl , Thomas Kern
CPC classification number: G11C7/06 , G11C7/062 , G11C7/065 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C13/00 , G11C16/349 , G11C17/00 , G11C29/028 , G11C29/50
Abstract: A method is suggested for determining a state of a cell structure, wherein the cell structure includes several memory cells, the method includes: (i) detecting a first condition in a predetermined number of memory cells; and (ii) determining the state of the cell structure by assigning a second condition to the memory cells that do not show the first condition.
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公开(公告)号：US09672941B1
公开(公告)日：2017-06-06
申请号：US15018264
申请日：2016-02-08
Applicant: Infineon Technologies AG
Inventor： Giacomo Curatolo , Thomas Kern
CPC classification number: G11C29/50 , G11C7/00 , G11C7/062 , G11C7/067 , G11C7/16 , G11C29/12005 , G11C29/1201 , G11C2029/5004 , G11C2029/5006 , G11C2207/063
Abstract: A circuit having a memory element coupled between and having a full voltage between two supply rails; and a detection unit coupled to the memory element and configured to maintain a substantially constant biasing of the memory element while simultaneously detecting current flow through the memory element.
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69.发明授权System and method to emulate an electrically erasable programmable read-only memory 有权用于模拟电可擦除可编程只读存储器的系统和方法公开(公告)号：US09569354B2
公开(公告)日：2017-02-14
申请号：US13957604
申请日：2013-08-02
Applicant: Infineon Technologies AG
Inventor： Ulrich Backhausen , Thomas Kern , Thomas Nirschl , Jens Rosenbusch , Xiangting Bi , Edvin Paparisto
CPC classification number: G06F12/0246 , G06F11/1048 , G06F12/0238 , G06F12/0292 , G06F2212/1032 , G06F2212/7201 , G06F2212/7207 , G11C2029/1806
Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.
Abstract translation: 本公开涉及一种电子存储器系统，更具体地，涉及一种用于模拟电可擦除可编程只读存储器的系统，以及用于模拟电可擦除可编程只读存储器的方法。 根据本公开的实施例，提供了一种用于模拟电可擦除可编程只读存储器的系统，所述系统包括第一存储器部分和第二存储器部分，其中第一存储器部分包括多个存储位置，其被配置为存储 数据被分割成多个数据段，并且其中第二存储器部分被配置为存储将存储在第一存储器部分中的数据段的物理地址映射到数据段的逻辑地址的信息。
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公开(公告)号：US09405618B2
公开(公告)日：2016-08-02
申请号：US14289311
申请日：2014-05-28
Applicant: Infineon Technologies AG
Inventor： Thomas Rabenalt , Ulrich Backhausen , Thomas Kern , Michael Goessel
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1012 , G11C16/10 , G11C16/26 , G11C29/52 , G11C2029/0411 , H03M13/13
Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.
Abstract translation: 公开了一种用于访问非易失性存储器的方法和存储器控制器。 该方法包括读取非易失性存储器的第一存储器区域，确定第一存储器区域是否包含预定数据模式，其中预定数据模式对至少第一存储区域确定的所得到的纠错数据没有影响。 该方法基于第一存储器区域中的预定数据模式的存在来评估非易失性存储器的第二存储器区域的数据状态，其中数据状态指示是否存在有效数据中的至少一个 第二存储器区域以及第二存储器区域是否可写入。
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