公开(公告)号：US08673774B2

公开(公告)日：2014-03-18

申请号：US13051501

申请日：2011-03-18

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a method for forming a via in a substrate. The method includes the following steps: (a) providing a substrate; (b) forming a groove that has a side wall and a bottom wall on a first surface of the substrate; (c) forming a first conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming a center insulating material in the central groove; (e) forming an annular groove that surrounds the first conductive metal on the first surface of the substrate; (f) forming a first insulating material in the annular groove; and (g) removing part of the substrate to expose the first conductive metal, the center insulating material and the first insulating material.

Abstract translation: 本发明涉及一种在衬底中形成通孔的方法。 该方法包括以下步骤：（a）提供衬底; （b）在基板的第一表面上形成具有侧壁和底壁的凹槽; （c）在所述槽的侧壁和底壁上形成第一导电金属，以形成中心槽; （d）在所述中央槽中形成中心绝缘材料; （e）在所述基板的第一表面上形成围绕所述第一导电金属的环形槽; （f）在所述环形槽中形成第一绝缘材料; 和（g）去除所述衬底的一部分以暴露所述第一导电金属，所述中心绝缘材料和所述第一绝缘材料。

公开(公告)号：US08546255B2

公开(公告)日：2013-10-01

申请号：US12849692

申请日：2010-08-03

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L21/768

CPC classification number: H01L21/76898

Abstract: The present invention relates to a method for forming vias in a semiconductor substrate, including the following steps: (a) providing a semiconductor substrate having a first surface and a second surface; (b) forming a groove on the semiconductor substrate; (c) filling the groove with a conductive metal; (d) removing part of the semiconductor substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the semiconductor substrate; and (e) forming an insulating material in the accommodating space. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.

Abstract translation: 本发明涉及一种在半导体衬底中形成通孔的方法，包括以下步骤：（a）提供具有第一表面和第二表面的半导体衬底; （b）在半导体衬底上形成沟槽; （c）用导电金属填充凹槽; （d）去除围绕所述导电金属的所述半导体衬底的一部分，其中所述导电金属被保持以在所述导电金属和所述半导体衬底之间形成容纳空间; 和（e）在容纳空间中形成绝缘材料。 以这种方式，可以在容纳空间中形成更厚的绝缘材料，并且容纳空间中的绝缘材料的厚度是均匀的。

公开(公告)号：US08466553B2

公开(公告)日：2013-06-18

申请号：US12902840

申请日：2010-10-12

Applicant: Bing-Hong Cheng ,  Meng-Jen Wang

Inventor： Bing-Hong Cheng ,  Meng-Jen Wang

IPC: H01L23/48

CPC classification number: H01L24/11 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/14181 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a conductive element. The conductive element is disposed on a protruded conductive via and liner, and covers a sidewall of the liner. Whereby, the conductive element can protect the protruded conductive via and liner from being damaged. Further, the size of the conductive element is large, thus it is easy to perform a probe test process.

Abstract translation: 本发明涉及半导体器件和具有该半导体器件的半导体封装。 半导体器件包括导电元件。 导电元件设置在突出的导电通孔和衬垫上，并且覆盖衬套的侧壁。 由此，导电元件可以保护突出的导电通孔和衬垫不被损坏。 此外，导电元件的尺寸大，因此容易进行探针测试处理。

公开(公告)号：US08390129B2

公开(公告)日：2013-03-05

申请号：US12945134

申请日：2010-11-12

Applicant: Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chung-Hsi Wu ,  Meng-Jen Wang

Inventor： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chung-Hsi Wu ,  Meng-Jen Wang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/544 ,  H01L23/481 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/16146

Abstract: The present invention relates to a semiconductor device with a plurality of mark through substrate vias, including a semiconductor substrate, a plurality of original through substrate vias and a plurality of mark through substrate vias. The original through substrate vias and the mark through substrate vias are disposed in the semiconductor substrate and protrude from the backside surface of the semiconductor substrate. The mark through substrate vias are added at a specific position and/or in a specific pattern and serve as a fiducial mark, which facilitates identifying the position and direction on the backside surface. Thus, the redistribution layer (RBL) or the special equipment for achieving the backside alignment (BSA) is not necessary.

Abstract translation: 本发明涉及具有多个标记通过衬底通孔的半导体器件，包括半导体衬底，多个原始通过衬底通孔和多个通过衬底通孔的标记。 原始通过衬底通孔和通过衬底通孔的标记设置在半导体衬底中并从半导体衬底的背面突出。 通过基板通孔的标记在特定位置和/或特定图案上添加，并且用作基准标记，这有助于识别背面上的位置和方向。 因此，不需要再分配层（RBL）或用于实现背侧对准（BSA）的专用设备。

公开(公告)号：US08310063B2

公开(公告)日：2012-11-13

申请号：US12907028

申请日：2010-10-19

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/11001 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor package structure including a substrate, a first chip, a second chip, and an interposer is provided. The substrate has a carrying surface and an opposite bottom surface. The first chip disposed on the carrying surface has a first surface and an opposite second surface. The second surface faces the substrate. The first chip has a plurality of through silicon vias (TSVs) and a plurality of first pads and second pads on the first surface. The first pads are electrically connected to the corresponding TSVs. The TSVs are electrically connected to the substrate. The second chip disposed above the first chip exposes a portion of the first surface. The second chip is electrically connected to the corresponding TSVs. The interposer is disposed on the first surface. Top surfaces of the interposer and the second chip are substantially aligned with each other. The interposer is bonded to the second pads.

Abstract translation: 提供了包括衬底，第一芯片，第二芯片和插入器的半导体封装结构。 衬底具有承载表面和相对的底表面。 布置在承载表面上的第一芯片具有第一表面和相对的第二表面。 第二表面面向衬底。 第一芯片具有多个穿通硅通孔（TSV）和第一表面上的多个第一焊盘和第二焊盘。 第一焊盘电连接到相应的TSV。 TSV电连接到基板。 设置在第一芯片上方的第二芯片暴露第一表面的一部分。 第二芯片电连接到相应的TSV。 插入器设置在第一表面上。 插入器和第二芯片的顶表面基本上彼此对准。 插入器结合到第二焊盘。

公开(公告)号：US20120086131A1

公开(公告)日：2012-04-12

申请号：US13092866

申请日：2011-04-22

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/147 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor element having conductive vias and a semiconductor package having a semiconductor element with conductive vias and a method for making the same. The semiconductor element having conductive vias includes a silicon substrate and at least one conductive via. The thickness of the silicon substrate is substantially in a range from 75 to 150 μm. The conductive via includes a first insulation layer and a conductive metal, and the thickness of the first insulation layer is substantially in a range from 5 to 19 μm. Using the semiconductor element and the semiconductor package of the present invention, the electrical connection between the conductive via and the other element can be ensured, and the electrical connection between the silicon substrate and the other semiconductor element can be ensured, so as to raise the yield rate of a product. Moreover, by employing the method of the present invention, warpage and shift of the silicon substrate can be avoided during the reflow process, so as to conduct the reflow process only a single time in the method of the present invention, thereby simplifying the subsequent process and reducing cost.

Abstract translation: 本发明涉及具有导电通孔的半导体元件和具有导电通孔的半导体元件的半导体封装及其制造方法。 具有导电通孔的半导体元件包括硅衬底和至少一个导电通路。 硅衬底的厚度基本上在75至150μm的范围内。 导电通孔包括第一绝缘层和导电金属，并且第一绝缘层的厚度基本上在5至19μm的范围内。 通过使用本发明的半导体元件和半导体封装，能够确保导电性通路与其他元件之间的电连接，能够确保硅基板与其他半导体元件之间的电连接，从而提高 产品的产率。 此外，通过采用本发明的方法，可以在回流工艺期间避免硅衬底的翘曲和偏移，从而在本发明的方法中仅进行一次回流处理，从而简化后续工艺 并降低成本。

公开(公告)号：US08039393B2

公开(公告)日：2011-10-18

申请号：US13088954

申请日：2011-04-18

Applicant: Meng-Jen Wang ,  Chien-Yu Chen

Inventor： Meng-Jen Wang ,  Chien-Yu Chen

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of the silicon substrate is removed to form a ring hole and a silicon pillar surrounded by the silicon pillar. Then, a photosensitive material is disposed in the ring hole, wherein the photosensitive material is insulating. After that, the silicon pillar is removed, such that the ring hole forms a through hole and the photosensitive material covers a lateral wall of the through hole. Lastly, the conductive material is disposed in the through hole, wherein the outer surface of the conductive material is surrounded by the photosensitive material.

Abstract translation: 提供半导体结构，半导体结构的制造方法以及半导体封装。 制造半导体结构的方法包括以下步骤。 首先，提供硅基板。 接下来，去除硅衬底的一部分以形成由硅柱包围的环形孔和硅柱。 然后，感光材料设置在环形孔中，其中感光材料是绝缘的。 之后，去除硅柱，使得环孔形成通孔，并且感光材料覆盖通孔的侧壁。 最后，导电材料设置在通孔中，其中导电材料的外表面被感光材料包围。

公开(公告)号：US20110171829A1

公开(公告)日：2011-07-14

申请号：US13051501

申请日：2011-03-18

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L21/28

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method for forming a via in a substrate includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a first conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming a center insulating material in the central groove; (e) forming an annular groove that surrounds the first conductive metal on the first surface of the substrate; (f) forming a first insulating material in the annular groove; and (g) removing part of the second surface of the substrate to expose the first conductive metal, the center insulating material and the first insulating material. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even.

Abstract translation: 本发明涉及一种用于在基板和具有通孔的基板上形成通孔的方法。 在衬底中形成通孔的方法包括以下步骤：（a）提供具有第一表面和第二表面的衬底; （b）在所述基板的第一表面上形成具有侧壁和底壁的凹槽; （c）在所述槽的侧壁和底壁上形成第一导电金属，以形成中心槽; （d）在所述中央槽中形成中心绝缘材料; （e）在所述基板的第一表面上形成围绕所述第一导电金属的环形槽; （f）在所述环形槽中形成第一绝缘材料; 和（g）去除衬底的第二表面的一部分以暴露第一导电金属，中心绝缘材料和第一绝缘材料。 结果，可以在通孔中形成更厚的绝缘材料，并且通孔中的绝缘材料的厚度是均匀的。

公开(公告)号：US07811858B2

公开(公告)日：2010-10-12

申请号：US12185879

申请日：2008-08-05

Applicant: Meng-Jen Wang ,  Wei-Chung Wang

Inventor： Meng-Jen Wang ,  Wei-Chung Wang

IPC: H01L21/48 ,  H01L21/50

CPC classification number: H01L23/5389 ,  H01L21/481 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2224/82 ,  H01L2924/00

Abstract: A package and the method for making the same, and a stacked package, the method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement.

Abstract translation: 一种包装及其制造方法以及堆叠包装，制造包装的方法包括以下步骤：（a）提供具有多个平台的载体; （b）提供多个骰子，并将骰子放置在平台上; （c）进行回流处理，使得骰子在平台上自对准; （d）在骰子之间的间隙中形成模塑料，和（e）进行切割处理以便形成多个包装。 由于在回流过程中骰子在平台上自对准，所以精度低的贴片机可以实现高精度的放置。

公开(公告)号：US20090035931A1

公开(公告)日：2009-02-05

申请号：US12183128

申请日：2008-07-31

Applicant: Meng-Jen Wang

Inventor： Meng-Jen Wang

IPC: H01L21/4763

CPC classification number: H01L21/76898

Abstract: The present invention relates to a method for forming vias in a substrate, comprising the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a photo resist layer on the first surface of the substrate; (c) forming a pattern on the photo resist layer; (d) forming a groove and a pillar in the substrate according to the pattern, wherein the groove surrounds the pillar; (e) forming a polymer in the groove of the substrate; (f) removing the pillar of the substrate to form an accommodating space; (g) forming a conductive metal in the accommodating space; and (h) removing part of the second surface of the substrate to expose the conductive metal and the polymer. As a result, thicker polymer can be formed in the groove, and the thickness of the polymer in the groove is uniform.

Abstract translation: 本发明涉及一种在衬底中形成通孔的方法，包括以下步骤：（a）提供具有第一表面和第二表面的衬底; （b）在所述基板的第一表面上形成光致抗蚀剂层; （c）在光致抗蚀剂层上形成图案; （d）根据图案在基板中形成凹槽和柱，其中凹槽围绕柱; （e）在基材的槽中形成聚合物; （f）移除基板的支柱以形成容纳空间; （g）在容纳空间中形成导电金属; 和（h）去除衬底的第二表面的一部分以暴露导电金属和聚合物。 结果，可以在沟槽中形成较厚的聚合物，并且沟槽中聚合物的厚度是均匀的。