公开(公告)号：US20140342476A1

公开(公告)日：2014-11-20

申请号：US14450998

申请日：2014-08-04

Applicant: Micron Technology, Inc.

Inventor： Lee Choon Kuan ,  David J. Corisis ,  Chin Hui Chong

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/00

CPC classification number: H01L24/92 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/49531 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92127 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. Terminal pads of the interposer substrate may be electrically connected to either or both of a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. Additional components, active, passive or both, may be connected to pads of the two-dimensional array to provide a system-in-a-package. Lead fingers of a lead frame may be superimposed on the opposing side of the interposer substrate, bonded directly to the land grid array land and wire bonded to pads as desired for repair or to ease routing problems on the interposer. The land grid array package may be mounted to a carrier substrate, and the lands wire bonded to conductive pads on the carrier substrate. Methods of fabrication are also disclosed.

Abstract translation: 半导体器件封装包括焊盘栅格阵列封装。 至少一个半导体管芯安装到插入器衬底上，其中半导体管芯的接合焊盘连接到与至少一个半导体管芯在内插器衬底的同一侧上的端子焊盘。 插入器基板的端子焊盘可以电连接到焊盘的外围阵列图案中的一个或两个以及中心的二维阵列阵列图案，两个阵列图案位于至少从中间层基板的相对侧起至少 一个半导体芯片。 可以将主动，被动或两者的附加组件连接到二维阵列的焊盘以提供系统级封装。 引线框架的引脚可以叠置在插入器基板的相对侧上，直接接合到焊盘栅格阵列焊盘，并且焊接到焊盘上，以便修理或者简化插入器上的布线问题。 焊盘阵列封装可以安装到载体衬底上，焊盘引线键合到载体衬底上的导电焊盘上。 还公开了制造方法。

公开(公告)号：US20130252354A1

公开(公告)日：2013-09-26

申请号：US13898004

申请日：2013-05-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC: H01L21/56

CPC classification number: H01L23/053 ,  H01L21/56 ,  H01L21/561 ,  H01L22/10 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49805 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06503 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

Abstract translation: 本文公开了堆叠的微电子器件和用于制造这种器件的方法。 在一个实施例中，堆叠的微电子器件组件可以包括包括第一插入器衬底的第一已知的良好封装的微电子器件。 第一管芯和第一穿通管互连件电耦合到第一插入器衬底。 第一壳体至少部分地封装第一装置，使得每个第一互连件的一部分在第一壳体的顶部可接近。 第二已知的良好封装的微电子器件以堆叠配置耦合到第一器件。 第二器件可以包括具有多个第二插入器焊盘的第二插入器衬底和与第二插入器衬底电耦合的第二管芯。 第一互连的暴露部分电耦合到对应的第二插入器焊盘。

公开(公告)号：US12148736B2

公开(公告)日：2024-11-19

申请号：US17592065

申请日：2022-02-03

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L25/065 ,  H01L25/00

Abstract: Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.

公开(公告)号：US20240304598A1

公开(公告)日：2024-09-12

申请号：US18424693

申请日：2024-01-26

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Seng Kim Dalson Ye ,  Hong Wan Ng ,  Kelvin Tan Aik Boo ,  Ling Pan ,  See Hiong Leow

IPC: H01L25/065 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H10B80/00 ,  H01L2225/06506

Abstract: A microelectronic device includes a controller device, a first die vertically overlying the controller device, a second die vertically overlying the first die, and a wire. The first die includes a first pad horizontally separated from a horizontal center of the controller device by a first distance. The second die includes a second pad horizontally separated from the horizontal center of the controller device by a second distance larger than the first distance. The wire contacts the first pad of the first die and the second pad of the second die. Memory device packages and electronic systems are also disclosed.

公开(公告)号：US20240071880A1

公开(公告)日：2024-02-29

申请号：US17897155

申请日：2022-08-27

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/16 ,  H01L24/16 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.

公开(公告)号：US11894289B2

公开(公告)日：2024-02-06

申请号：US17982397

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L29/76 ,  H01L29/00 ,  H01L23/48 ,  H01L27/08 ,  H01L49/02 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L27/0805 ,  H01L28/40

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

公开(公告)号：US20230369291A1

公开(公告)日：2023-11-16

申请号：US18225369

申请日：2023-07-24

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Chin Hui Chong ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/50 ,  H01L2225/06572 ,  H01L2225/0651 ,  H01L2224/48227 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

公开(公告)号：US20230282588A1

公开(公告)日：2023-09-07

申请号：US18111517

申请日：2023-02-17

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L23/538 ,  H10B80/00 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16 ,  H01L23/498

CPC classification number: H01L23/5382 ,  H10B80/00 ,  H01L21/4853 ,  H01L24/48 ,  H01L24/32 ,  H01L24/73 ,  H01L24/16 ,  H01L25/162 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2924/1438 ,  H01L2924/1433 ,  H01L2224/48147 ,  H01L2224/48229 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265

Abstract: Semiconductor device assemblies having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device assembly includes a substrate, a controller, and an interposer. The substrate has a top surface and a bottom surface. A cavity extends below the top surface. The controller has a first pin-out pattern. The interposer has a top surface with the first pin-out pattern that is directly connected to the controller and a bottom surface that has a second pin-out pattern. The interposer interconnects the first and second pin-out patterns, and the interposer and the second pin-out pattern are configured to be directly attached to a surface of the substrate in the cavity.

公开(公告)号：US20230066375A1

公开(公告)日：2023-03-02

申请号：US17412604

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: Semiconductor devices including thermally conductive structures are disclosed herein. A heat transfer structure may be thermally coupled to a semiconductor device and directly attached to a signaling layer of a substrate. The heat transfer structure may be configured to remove thermal energy from the semiconductor device and transfer at least a portion of the removed thermal energy directly into the signaling layer for dissipation within the substrate, for transfer through the substrate and out of a corresponding apparatus, or a combination thereof.

公开(公告)号：US20220336419A1

公开(公告)日：2022-10-20

申请号：US17233129

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Seng Kim Ye ,  Chin Hui Chong ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.