公开(公告)号：US09412675B2

公开(公告)日：2016-08-09

申请号：US14281449

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang ,  James M. Derderian

IPC: H01L25/065 ,  H01L25/04 ,  H01L23/40 ,  H01L23/00 ,  H01L23/498 ,  H01L25/075 ,  H01L23/34 ,  H01L23/367 ,  H01L23/42

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/34 ,  H01L23/3675 ,  H01L23/4012 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/11 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/05032 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.

Abstract translation: 具有改进的导电性质的互连结构在本文中公开。 在一个实施例中，互连结构可以包括耦合到第一半导体管芯的第一导电构件和耦合到第二半导体管芯的第二导电构件。 第一导电构件包括限定凹陷的凹陷表面。 第二导电构件至少部分地延伸到第一导电构件的凹陷中。 凹陷内的粘合材料可以至少部分地包封第二导电构件，从而将第二导电构件结合到第一导电构件。

公开(公告)号：US20160225695A1

公开(公告)日：2016-08-04

申请号：US14608751

申请日：2015-01-29

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC: H01L23/48 ,  H01L21/288 ,  H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/3212 ,  H01L21/7684 ,  H01L21/76898

Abstract: Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

Abstract translation: 公开了通过硅通孔（TSV）的均匀背侧曝光的系统和方法。 在一个实施例中，半导体器件包括具有形成在其上的电路元件的正面和与前侧相对的背面的衬底。 TSV在基板的正面和背面之间延伸，并且虚设特征设置在基板的背面上方，虚拟特征与TSV横向间隔开并与TSV基本上共面。 在另一个实施例中，半导体器件包括具有穿过其形成的TSV的衬底，其中控制材料设置在衬底的背面上，TSV与控制材料基本上共面。

公开(公告)号：US20160172242A1

公开(公告)日：2016-06-16

申请号：US15050858

申请日：2016-02-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

公开(公告)号：US09318438B2

公开(公告)日：2016-04-19

申请号：US14679845

申请日：2015-04-06

Applicant: Micron Technology, Inc.

Inventor： Mark A. Bossler ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Randall S. Parker

IPC: H01L23/532 ,  H01L23/538 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L23/53238 ,  H01L21/02068 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for selectively removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Abstract translation: 一种用于从衬底选择性地去除材料的方法，而不损坏铜填充通孔并且至少部分地延伸通过衬底。 该方法包括氧化包括基底和至少一个铜特征的半导体结构，并且使用包含SF 6的蚀刻剂去除一部分基底，而不在至少一个铜特征上形成硫化铜。 还公开了另外的方法，以及由这些方法制备的半导体结构。

公开(公告)号：US09299663B2

公开(公告)日：2016-03-29

申请号：US14281362

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L23/04 ,  H01L23/544 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，用于将电子特征对准到贯通基板通孔的方法包括形成具有围绕TSV的至少一部分的壁的自对准对准特征，并将光刻工具对准自对准对准特征。 在一些实施例中，自对准对准特征由设备背面的种子材料的形貌定义。

公开(公告)号：US20160013114A1

公开(公告)日：2016-01-14

申请号：US14330900

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/34 ,  H01L23/10 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/4275 ,  H01L23/473 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/92125 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1627 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a first semiconductor die electrically mounted to the package support substrate, and a plurality of second semiconductor dies. The first die has a stacking site and a peripheral region extending laterally from the stacking site, and the bottom second semiconductor die is attached to the stacking site of the first die. The assembly further includes (a) a thermal transfer structure attached to the peripheral region of the first die that has a cavity in which the second dies are positioned and an inlet, and (b) an underfill material in the cavity. The underfill material has a fillet between the second semiconductor dies caused by injecting the underfill material into the cavity through the inlet port of the casing.

Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，电气安装到封装支撑衬底的第一半导体管芯和多个第二半导体管芯。 第一模具具有堆叠位置和从堆叠位置​​横向延伸的周边区域，并且底部第二半导体管芯附接到第一管芯的堆叠位置。 组件还包括（a）附接到第一模具的周边区域的热转印结构，其具有第二模具所在的空腔和入口，以及（b）空腔中的底部填充材料。 底部填充材料在第二半导体管芯之间具有由底部填充材料通过壳体的入口注入空腔而引起的圆角。

公开(公告)号：US20150333026A1

公开(公告)日：2015-11-19

申请号：US14281449

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang ,  James M. Derderian

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/34 ,  H01L23/3675 ,  H01L23/4012 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/11 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/05032 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.

Abstract translation: 具有改进的导电性质的互连结构在本文中公开。 在一个实施例中，互连结构可以包括耦合到第一半导体管芯的第一导电构件和耦合到第二半导体管芯的第二导电构件。 第一导电构件包括限定凹陷的凹陷表面。 第二导电构件至少部分地延伸到第一导电构件的凹陷中。 凹陷内的粘合材料可以至少部分地包封第二导电构件，从而将第二导电构件结合到第一导电构件。

公开(公告)号：US20150333014A1

公开(公告)日：2015-11-19

申请号：US14281362

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，用于将电子特征对准到贯通基板通孔的方法包括形成具有围绕TSV的至少一部分的壁的自对准对准特征，并将光刻工具对准自对准对准特征。 在一些实施例中，自对准对准特征由设备背面的种子材料的形貌定义。

公开(公告)号：US20150097301A1

公开(公告)日：2015-04-09

申请号：US14569272

申请日：2014-12-12

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/50 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/78 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12042 ,  H01L2924/00012

Abstract: Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. Some methods include forming a polymeric material comprising Si—O—Si over a first substrate, removing a portion of the polymeric material, and adhesively bonding another substrate to the first substrate. Structures include a polymeric material comprising Si—O—Si disposed over a first substrate, an adhesive material disposed over the first substrate and at least a portion of the polymeric material, and a second substrate disposed over the adhesive material.

公开(公告)号：US20210125899A1

公开(公告)日：2021-04-29

申请号：US17140610

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Bradley R. Bitz ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L23/427 ,  H01L25/065 ,  H01L23/46 ,  H01L23/473 ,  H01L23/42 ,  H01L23/433

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.