公开(公告)号：US09257648B2

公开(公告)日：2016-02-09

申请号：US14173096

申请日：2014-02-05

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: G11C11/00 ,  H01L45/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/165

Abstract: Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable material having two compositionally different regions. A concentration of ions and/or ion-vacancies may be altered in at least one of the regions to change a memory state of the memory cell and to simultaneously form a pn diode. Some embodiments include memory cells having programmable material with two compositionally different regions, and having ions and/or ion-vacancies diffusible into at least one of the regions. The memory cell has a memory state in which the first and second regions are of opposite conductivity type relative to one another.

Abstract translation: 一些实施例包括其中存储单元形成为在第一和第二访问线之间具有可编程材料的方法，其中可编程材料具有两个组成上不同的区域。 可以在至少一个区域中改变离子和/或离子空位的浓度以改变存储器单元的存储状态并同时形成pn二极管。 一些实施例包括具有两个组成不同区域的可编程材料并且具有可扩散到至少一个区域中的离子和/或离子空位的存储器单元。 存储单元具有其中第一和第二区域相对于彼此具有相反导电类型的存储状态。

公开(公告)号：US09257430B2

公开(公告)日：2016-02-09

申请号：US14680431

申请日：2015-04-07

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: H01L45/00 ,  H01L27/102 ,  G11C13/00 ,  H01L27/24 ,  H01L29/872 ,  H01L29/66

CPC classification number: H01L45/1608 ,  G11C13/003 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/6609 ,  H01L29/872

Abstract: Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode.

Abstract translation: 存储器件结构包括平行于第二列线延伸的第一列线，第一列线在第二列线之上; 在第二列线上方的行线，并垂直于第一列线和第二列线延伸; 存储器材料，其设置成选择性地和可逆地配置为两种或更多种不同电阻状态之一; 第一二极管，被配置为经由所述存储材料在所述第一列线和所述行线之间传导第一电流; 以及第二二极管，被配置为经由存储器材料在第二列线和行线之间传导第二电流。 在一些实施例中，第一二极管是具有半导体阳极和金属阴极的肖特基二极管，第二二极管是具有金属阳极和半导体阴极的肖特基二极管。

公开(公告)号：US20150372227A1

公开(公告)日：2015-12-24

申请号：US14840252

申请日：2015-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

Abstract: Memory cells useful in phase change memory include a phase change material between first and second electrode and having a surface facing a surface of the second electrode. The second electrode comprises a plurality of portions of material, each portion having a respective distance from the surface of the phase change material and each portion having a respective resistivity. A portion of the plurality of portions of material farthest from the surface of the phase change material has a lowest resistivity and a portion of the plurality of portions of material closest to the surface of the phase change material has a highest resistivity. The resistivity of each individual portion is lower than the resistivity of each portion located closer to the surface of the phase change material, and higher than the resistivity of each portion located farther from the surface of the phase change material.

Abstract translation: 在相变存储器中有用的存储器单元包括第一和第二电极之间的相变材料，并且具有面向第二电极的表面的表面。 第二电极包括多个材料部分，每个部分具有与相变材料的表面相对应的距离，并且每个部分具有相应的电阻率。 离相变材料表面最远的多个材料部分的一部分具有最低的电阻率，并且最靠近相变材料表面的多个材料部分的一部分具有最高的电阻率。 每个单独部分的电阻率低于位于相变材料表面附近的每个部分的电阻率，并且高于位于离相变材料表面更远的每个部分的电阻率。

公开(公告)号：US09184385B2

公开(公告)日：2015-11-10

申请号：US14276198

申请日：2014-05-13

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: G11C11/00 ,  H01L45/00 ,  H01L27/102 ,  H01L27/24 ,  G11C5/06 ,  G11C5/02 ,  H01L21/302 ,  G11C13/00

CPC classification number: H01L45/1608 ,  G11C5/02 ,  G11C5/06 ,  G11C13/0004 ,  G11C2213/71 ,  H01L21/302 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165

Abstract: An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed.

Abstract translation: 非易失性存储单元的阵列包括多个垂直堆叠的非易失性存储单元层。 层分别包括第一多个水平取向的第一电极线和相对于第一电极线交叉的第二多个水平取向的第二电极线。 存储单元的个体包括第一电极线和第二电极线中的一个之间的交叉的一个以及其间的材料。 具体地说，与可编程材料串联的选择装置以及与可编程材料和选择装置之间串联的当前导电材料与第一和第二电极线中交叉的那些串联地提供。 材料和装置可以被定向成在限定的水平和垂直方向上的主要电流流动。 公开了方法和其他实现和方面。

公开(公告)号：US09165627B2

公开(公告)日：2015-10-20

申请号：US13926397

申请日：2013-06-25

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: G11C11/00 ,  G11C11/16 ,  H01L43/08 ,  H01L29/66 ,  H01L43/02

CPC classification number: G11C11/16 ,  G11C11/161 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08

Abstract: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack including a nonmagnetic material between a first ferromagnetic material and a second ferromagnetic material and a soft magnetic material surrounding at least a portion of the annular STT stack.

Abstract translation: 本文描述了旋转转矩传递（STT）存储单元结构和方法。 一个或多个STT存储器单元结构包括在第一铁磁材料和第二铁磁材料之间包括非磁性材料的环形STT堆叠和围绕环形STT堆叠的至少一部分的软磁材料。

公开(公告)号：US09064793B2

公开(公告)日：2015-06-23

申请号：US14184142

申请日：2014-02-19

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.

Abstract translation: 本文描述了与相变单元结构相关联的方法和装置。 在一个或多个实施例中，形成相变单元结构的方法包括形成包括底电极的衬底突起，在衬底突起上形成相变材料，在相变材料上形成导电材料，以及去除部分 的导电材料和相变材料的一部分以形成封装的堆叠结构。

公开(公告)号：US09064572B2

公开(公告)日：2015-06-23

申请号：US13847205

申请日：2013-03-19

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Wenzhou Chen

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/10 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C8/10 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2013/009 ,  G11C2013/0092

Abstract: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.

Abstract translation: 本文描述了与多电平相变存储器单元相关联的方法，装置和系统。 本公开的一个或多个实施例包括通过将相变存储器单元置于复位状态来操作相变存储器件，并将所选择的编程脉冲施加到相变存储器单元，以将该单元编程为多个 在复位状态和与单元相关联的设置状态之间的中间状态。 所选择的编程脉冲包括在特定持续时间内施加的最高幅度，该特定持续时间取决于存储器单元将被编程的中间状态数目中的哪一个。

公开(公告)号：US20150131362A1

公开(公告)日：2015-05-14

申请号：US14599905

申请日：2015-01-19

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  C07D213/81 ,  C07D401/06 ,  C07D401/12 ,  C07D401/14 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/1021

Abstract: Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further, methods and devices for addressing and accessing cells are shown that provide a simple and efficient way to manage devices with multiple cells associated with each access transistor. Examples of multiple cell devices include phase change memory devices with multiple cells associated with each access transistor.

Abstract translation: 显示了所描述的存储器件和方法，其提供了改进，包括改进的诸如读取和写入等操作的单元隔离。 此外，示出了用于寻址和访问单元的方法和设备，其提供用于管理具有与每个存取晶体管相关联的多个单元的器件的简单且有效的方式。 多个单元设备的示例包括具有与每个存取晶体管相关联的多个单元的相变存储器件。

公开(公告)号：US20150041754A1

公开(公告)日：2015-02-12

申请号：US14524435

申请日：2014-10-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Kristy A. Campbell

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625 ,  Y10S977/773

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.

公开(公告)号：US20140353571A1

公开(公告)日：2014-12-04

申请号：US14445669

申请日：2014-07-29

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691

Abstract: Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor.

Abstract translation: 本文描述了垂直晶体管相变存储器和处理相变存储器的方法。 一种或多种方法包括在垂直晶体管的至少一部分上形成电介质，在电介质上形成电极，并且在电极侧面的一部分和侧面的一部分上形成垂直条状的相变材料 的电介质沿着电极延伸并且电介质与垂直晶体管接触。