公开(公告)号：US20190340065A1

公开(公告)日：2019-11-07

申请号：US16516510

申请日：2019-07-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G06F12/06 ,  G11C16/04 ,  G06F12/02 ,  G11C16/10 ,  G11C11/56

Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure different blocks of the plurality of blocks of memory cells in different configurations, which can include blocks configured to include only groups of user data memory cells for storing user data, blocks configured to include only groups of overhead data memory cells for storing error correction code (ECC) data, and blocks configured to include groups of user data memory cells and groups of overhead data memory cells.

公开(公告)号：US09929967B2

公开(公告)日：2018-03-27

申请号：US14108599

申请日：2013-12-17

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Victor Y. Tsai ,  Peter Feeley ,  Neal A. Galbo ,  Robert N. Leibowitz

IPC: H04L12/801 ,  H04L12/807 ,  H04L29/08 ,  H04L1/18

CPC classification number: H04L47/34 ,  H04L1/1867 ,  H04L47/27 ,  H04L69/324

Abstract: The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.

公开(公告)号：US09766830B2

公开(公告)日：2017-09-19

申请号：US15171677

申请日：2016-06-02

Applicant: Micron Technology, Inc.

Inventor： Krishnam R. Datla ,  William H. Radke ,  Robin Sarno ,  Laszlo Borbely-Bartis ,  Ken Kannampuzha

IPC: G11C8/16 ,  G06F3/06 ,  G11C5/14 ,  G11C16/30

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G11C5/14 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.

公开(公告)号：US09588697B2

公开(公告)日：2017-03-07

申请号：US14718461

申请日：2015-05-21

Applicant: Micron Technology, Inc.

Inventor： Peter Feeley ,  Robert N. Leibowitz ,  William H. Radke ,  Neal A. Galbo ,  Victor Y. Tsai

IPC: G06F13/28 ,  G06F3/00 ,  G06F3/06 ,  G06F13/38 ,  G06F13/32 ,  G06F13/42

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/28 ,  G06F13/32 ,  G06F13/385 ,  G06F13/4282

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract translation: 本公开包括用于控制存储器设备的方法，设备和系统。 用于控制存储器件实施例的一种方法包括将设备类相关信息和命令存储在主机系统存储器和主机控制器存储器中的一个或多个中，在主机控制器中的寄存器中设置指向该命令的指针， 通过主机控制器更多的主机系统内存和主机控制器内存与存储设备; 并用存储器件执行命令。

公开(公告)号：US09552257B2

公开(公告)日：2017-01-24

申请号：US15059367

申请日：2016-03-03

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  William H. Radke ,  Peter Feeley

IPC: G11C16/34 ,  G06F11/10 ,  G11C29/04 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C16/04 ,  G11C16/06

CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F11/1048 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/04 ,  G11C29/52

Abstract: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.

Abstract translation: 描述了用于存储器单元耦合补偿的方法和被配置为执行其的装置。 用于存储单元耦合补偿的一种或多种方法包括使用根据第一存储单元耦合补偿电压而改变的电压来确定存储单元的状态，对存储单元的状态执行错误检查，以及确定状态 使用响应于错误检查失败的根据第二存储器单元耦合补偿电压而改变的电压的存储器单元。

公开(公告)号：US20160217867A1

公开(公告)日：2016-07-28

申请号：US15091078

申请日：2016-04-05

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  William H. Radke

IPC: G11C16/34

CPC classification number: G11C16/34 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3418

Abstract: The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.

公开(公告)号：US20160154747A1

公开(公告)日：2016-06-02

申请号：US14992612

申请日：2016-01-11

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Victor Y. Tsai ,  James Cooke ,  Neal A. Galbo ,  Peter Feeley

IPC: G06F13/10 ,  G06F13/42

CPC classification number: G06F13/102 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/1684 ,  G06F13/4282 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

公开(公告)号：US09305659B2

公开(公告)日：2016-04-05

申请号：US14826298

申请日：2015-08-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3436 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3422

Abstract: A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window.

Abstract translation: 存储器件具有存储器单元的阵列和耦合到存储器单元阵列的控制器。 控制器被配置为在执行对存储器件执行的特定编程操作的一部分之后以及在执行对存储器件执行的特定编程操作的后续部分之后确定程序窗口。 控制器被配置为响应于由存储器单元的特定状态经历的程序干扰的量来确定程序窗口。 控制器被配置为使用所确定的程序窗口来执行在存储器设备上执行的特定编程操作的后续部分。

公开(公告)号：US09293214B2

公开(公告)日：2016-03-22

申请号：US14719519

申请日：2015-05-22

Applicant: Micron Technology, Inc.

Inventor： William H. Radke ,  Zhenlei Shen ,  Peter Feeley

IPC: G11C11/34 ,  G11C16/26 ,  G11C11/26 ,  G11C11/56 ,  G11C7/14 ,  G11C16/34 ,  G11C29/02 ,  G11C29/42 ,  G11C29/50

CPC classification number: G11C16/26 ,  G11C7/14 ,  G11C11/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50004

Abstract: The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.

公开(公告)号：US09229802B2

公开(公告)日：2016-01-05

申请号：US14156988

申请日：2014-01-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Shuba Swaminathan ,  Brady L. Keays

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1068

Abstract: Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption.

Abstract translation: 描述了通过对非系统ECC代码中的存储器行或块的数据位进行编码来促进存储器系统或设备中的数据的检测和校正的方法。 这允许本发明的存储器实施例利用降低复杂性的错误检测和校正硬件和/或例程来有效地检测和校正存储器的段（例如扇区，字线行或擦除块）中的损坏的用户数据。 用户数据不以存储器阵列中的明文格式存储，从而可以提高数据安全级别。 ECC代码分布在存储器段中的所有存储的数据中，增加ECC代码的鲁棒性及其对损坏或数据损坏的抵抗力。