公开(公告)号：US5995443A

公开(公告)日：1999-11-30

申请号：US262114

申请日：1999-03-04

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/006 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

公开(公告)号：US5915105A

公开(公告)日：1999-06-22

申请号：US979127

申请日：1997-11-26

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

公开(公告)号：US09195602B2

公开(公告)日：2015-11-24

申请号：US12529323

申请日：2008-03-19

Applicant: Craig Hampel ,  Mark Horowitz

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/12 ,  G11C29/00

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G11C2029/3202 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.

Abstract translation: 公开了一种存储器系统，其包括存储器控制器和限定第一存储器层级的第一组易失性存储器件。 第一组易失性存储器件设置在至少一个第一存储器模块上，该第一存储器模块以菊花链式配置耦合到存储器控制器。 模块中包含第一个集成电路缓冲器。 该系统具有定义第二存储器层级的第二组非易失性存储器件。 第二组非易失性存储器件设置在至少一个第二存储器模块上，其以菊花链式配置耦合到至少一个第一存储器模块。 第二模块包括第二集成电路缓冲装置。 该系统被配置为使得在存储器控制器和第二存储器层级之间传输的信号通过第一存储器层级。

公开(公告)号：US20140188966A1

公开(公告)日：2014-07-03

申请号：US13556710

申请日：2012-07-24

Applicant: Sameh Galal ,  Mark Horowitz

Inventor： Sameh Galal ,  Mark Horowitz

IPC: G06F7/487 ,  G06F7/485

CPC classification number: G06F7/5443 ,  G06F7/483 ,  G06F7/49947

Abstract: A floating-point fused multiply-add (FMA) unit embodied in an integrated circuit includes a multiplier circuit cascaded with an adder circuit to produce a result A*C+B. To decrease latency, the FMA includes accumulation bypass circuits forwarding an unrounded result of the adder to inputs of the close path and the far path circuits of the adder, and forwarding an exponent result in carry save format to an input of the exponent difference circuit. Also included in the FMA is a multiply-add bypass circuit forwarding the unrounded result to the inputs of the multiplier circuit. The adder circuit includes an exponent difference circuit implemented in parallel with the multiplier circuit; a close path circuit implemented after the exponent difference circuit; and a far path circuit implemented after the exponent difference circuit.

Abstract translation: 在集成电路中实现的浮点融合乘法（FMA）单元包括与加法器电路级联的乘法器电路，以产生结果A * C + B。 为了减少等待时间，FMA包括累加旁路电路，将加法器的未包围结果转发到加法器的关闭路径和远程路径电路的输入，并将指令结果以进位保存格式转发到指数差分电路的输入。 还包括在FMA中的是将不包围的结果转发到乘法器电路的输入的多路旁路电路。 加法器电路包括与乘法器电路并联实现的指数差电路; 在指数差分电路之后实现的闭路电路; 以及在指数差分电路之后实现的远程电路。

公开(公告)号：US20120324408A1

公开(公告)日：2012-12-20

申请号：US13399770

申请日：2012-02-17

Applicant: Ofer Shacham ,  Mark Horowitz ,  Stephen Richardson

Inventor： Ofer Shacham ,  Mark Horowitz ,  Stephen Richardson

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, an embodiment of the present invention fixes the top level system architecture, amortizes software and validation and design costs, and enables a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can “program” the individual inner components of the architecture. Unlike reconfigurable chips, a chip generator according to an embodiment of the present invention, compiles the program to create a customized chip. This compilation process occurs at elaboration time—long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level because additional components and logic can be added if the customization process requires it.

Abstract translation: 根据本发明实施例的芯片发生器将设计者的知识和设计权衡编成可用于创建许多不同芯片的模板。 像可重构设计一样，本发明的实施例解决了顶级系统架构，分摊软件和验证和设计成本，并为应用程序开发人员提供了丰富的系统仿真环境。 同时，在顶层以下，开发人员可以对架构的各个内部组件进行编程。 与可重构芯片不同，根据本发明的实施例的芯片发生器编译程序以创建定制的芯片。 这种编译过程在制造硅之前的时间很长。 结果是一个框架，可以在架构层面实现更多的定制生成的芯片，因为如果定制过程需要可以添加额外的组件和逻辑。

公开(公告)号：US20100115191A1

公开(公告)日：2010-05-06

申请号：US12529323

申请日：2008-03-19

Applicant: Craig Hampel ,  Mark Horowitz

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G11C2029/3202 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.

Abstract translation: 公开了一种存储器系统，其包括存储器控制器和限定第一存储器层级的第一组易失性存储器件。 第一组易失性存储器件设置在至少一个第一存储器模块上，该第一存储器模块以菊花链式配置耦合到存储器控制器。 模块中包含第一个集成电路缓冲器。 该系统具有定义第二存储器层级的第二组非易失性存储器件。 第二组非易失性存储器件设置在至少一个第二存储器模块上，其以菊花链式配置耦合到至少一个第一存储器模块。 第二模块包括第二集成电路缓冲装置。 该系统被配置为使得在存储器控制器和第二存储器层级之间传输的信号通过第一存储器层级。

公开(公告)号：US20090268804A1

公开(公告)日：2009-10-29

申请号：US12149157

申请日：2008-04-28

Applicant: Toshitsugu Kawashima ,  Mark Horowitz

Inventor： Toshitsugu Kawashima ,  Mark Horowitz

IPC: H04L27/01

CPC classification number: H04L25/03057 ,  H04L25/03235

Abstract: Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.

Abstract translation: 公开了一种延迟判定反馈序列估计器，其包括延迟判定反馈序列估计器主单元，该延迟判定反馈序列估计器主单元包括DDFSE计算单元组，其包括（L + M）DDFSE计算单元，其数量等于多个块中的每一个的长度，其中接收的数据符号 序列分为 其中（L + M）DDFSE计算单元以流水线配置连接以并行地执行块的延迟判定反馈序列估计; 以及边缘效应检测和校正电路，其检测由于处理分离块的延迟的判定反馈序列估计的边缘效应并校正相关的位错误。

公开(公告)号：US20080273940A1

公开(公告)日：2008-11-06

申请号：US11799570

申请日：2007-05-03

Applicant: Mark Horowitz

Inventor： Mark Horowitz

IPC: F16B35/06 ,  E06B3/30

CPC classification number: F16B35/06 ,  E06B2009/005 ,  F16B23/00 ,  F16B37/16

Abstract: A wing-bolt for holding panels or covers over openings for protection against intrusions during storms or bad weather.

Abstract translation: 一个翼形螺栓，用于在风暴或恶劣天气下保护面板或盖子以防止入侵。

公开(公告)号：US20080069561A1

公开(公告)日：2008-03-20

申请号：US11940199

申请日：2007-11-14

Applicant: Joseph Kahn ,  Mark Horowitz ,  Olav Solgaard ,  Shanhui Fan

Inventor： Joseph Kahn ,  Mark Horowitz ,  Olav Solgaard ,  Shanhui Fan

IPC: H04K3/00

CPC classification number: G02B6/4206 ,  G02B6/2861

Abstract: Optical signals are passed in an optical medium using an approach that facilitates the mitigation of interference. According to an example embodiment, a filtering-type approach is used with an optical signal conveyed in an optical fiber, such as a multimode fiber (MMF) or a multimode waveguide. Adaptive spatial domain signal processing, responsive to a feedback signal indicative of data conveyed in the multimode waveguide, is used to mitigate interference in optical signals conveyed in the multimode waveguide.

Abstract translation: 光信号通过使用有助于减轻干扰的方法在光学介质中传播。 根据示例实施例，滤波型方法与诸如多模光纤（MMF）或多模波导之类的光纤中传送的光信号一起使用。 响应于指示在多模波导中传送的数据的反馈信号的自适应空间域信号处理被用于减轻在多模波导中传送的光信号中的干扰。

公开(公告)号：US07333578B2

公开(公告)日：2008-02-19

申请号：US09862384

申请日：2001-05-22

Applicant: Ramin Farjad-Rad ,  Mark Horowitz

Inventor： Ramin Farjad-Rad ,  Mark Horowitz

IPC: H04L7/00

CPC classification number: H03L7/087 ,  H03L7/14 ,  H04L7/0337

Abstract: An input data sequence is sampled according to a sampling clock such that a first set of samples corresponds to data values and a second set of samples corresponds to edges between the data values. The phase error between data transitions in the input sequence and the sampled edges is determined based on amplitudes of the sampled edges. The sampling clock's phase is adjusted based on the determined phase error. Typically, the phase error is proportional to an amplitude of a sampled edge. Sampled edge amplitude values are added or subtracted, according to the direction of each transition about each edge to form an error value which indicates the amount phase error.

Abstract translation: 输入数据序列根据采样时钟采样，使得第一组样本对应于数据值，第二组样本对应于数据值之间的边。 基于采样边沿的幅度确定输入序列中的数据转换与采样边沿之间的相位误差。 采样时钟相位根据确定的相位误差进行调整。 通常，相位误差与采样边沿的幅度成比例。 根据每个边缘的每个转换的方向，对采样的边缘幅度值进行相加或相减，以形成指示量相位误差的误差值。