公开(公告)号：US20050267663A1

公开(公告)日：2005-12-01

申请号：US11072494

申请日：2005-03-07

申请人： Ken Naono ,  Masaaki Shimizu ,  Fumio Arakawa ,  Nobuyasu Kanekawa ,  Kohei Sakurai ,  Masatoshi Hoshino ,  Kentaro Yoshimura

发明人： Ken Naono ,  Masaaki Shimizu ,  Fumio Arakawa ,  Nobuyasu Kanekawa ,  Kohei Sakurai ,  Masatoshi Hoshino ,  Kentaro Yoshimura

IPC分类号： B60R16/02 ,  B60W10/00 ,  B60W10/02 ,  B60W10/04 ,  B60W10/06 ,  B60W10/10 ,  B60W10/12 ,  B60W10/18 ,  B60W10/184 ,  B60W10/20 ,  B60W10/22 ,  F02D45/00 ,  G05B13/02 ,  G06F17/00

CPC分类号： G05B13/024

摘要： To reduce the man-hour required in tuning control parameters, a vehicular control system of this invention comprises a user parameter input module, an external parameter input module, a plurality of objective functions, a policy setting module, and a policy node. The user parameter input module inputs a user parameter corresponding to an operation of a user. The external parameter input module inputs an external parameter resulting from an outside environment. The objective functions are set for each control characteristic respectively so as to calculate an internal parameter of each control target from the user parameter and the external parameter. The policy setting module sets policies indicating a control index of the user for the objective functions respectively. The policy node weights the objective functions on the basis of the policies, adjusts the internal parameter in accordance with the policy so that the internal parameter is optimized (minimized or maximized) among the objective functions, and issues a command to a control node corresponding to the internal parameter.

摘要翻译： 为了减少调谐控制参数所需的工时，本发明的车辆控制系统包括用户参数输入模块，外部参数输入模块，多个目标功能，策略设置模块和策略节点。 用户参数输入模块输入与用户的操作对应的用户参数。 外部参数输入模块输入外部环境引起的外部参数。 分别为每个控制特性设定目标函数，以从用户参数和外部参数计算每个控制目标的内部参数。 策略设置模块分别针对目标函数设置指示用户的控制索引的策略。 策略节点根据策略对目标函数进行加权，根据策略调整内部参数，使内部参数在目标函数中进行优化（最小化或最大化），并向对应的控制节点发出命令 内部参数。

公开(公告)号：US20050252272A1

公开(公告)日：2005-11-17

申请号：US11110697

申请日：2005-04-21

申请人： Tetsuro Otsuka ,  Atsushi Horikoshi ,  Nobuyasu Kanekawa ,  Shoji Sasaki

发明人： Tetsuro Otsuka ,  Atsushi Horikoshi ,  Nobuyasu Kanekawa ,  Shoji Sasaki

IPC分类号： G01D5/245 ,  G01D5/244 ,  G01W1/18

CPC分类号： G01D5/24461 ,  G01D5/24457

摘要： In a resolver digital converter comprising a resolver, a resolver digital conversion part, and an excitation signal generation part, the resolver digital converter for inputting an excitation signal generated in the excitation signal generation part to the resolver and inputting resolver signals outputted from the resolver to the resolver digital conversion part, a locus in which amplitude of a sine component signal among the resolver signals sin(θ), cos(θ) outputted from the resolver is plotted as the ordinate axis and amplitude of a cosine component signal is plotted as the abscissa axis is approximated by a polygon and when the locus matches with sides of the approximated polygon, it is determined that the resolver is in a normal state and when the locus does not match, it is determined that the resolver is in a failure state.

摘要翻译： 在包括分解器，分解器数字转换部分和激励信号生成部分的解算器数字转换器中，所述分解器数字转换器用于将在激励信号产生部分中产生的激励信号输入到旋转变压器，并将从旋转变压器输出的解算器信号输入到 旋转变压器数字转换部分将将从分解器输出的旋转变压器信号sin（θ），cos（theta）中的正弦分量信号的幅度绘制为纵轴和余弦分量信号的幅度的轨迹被绘制为 横坐标轴由多边形近似，并且当轨迹与近似多边形的边匹配时，确定解析器处于正常状态，并且当轨迹不匹配时，确定旋转变压器处于故障状态。

公开(公告)号：US06728904B2

公开(公告)日：2004-04-27

申请号：US10370518

申请日：2003-02-24

申请人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

发明人： Nobuyasu Kanekawa ,  Hirokazu Ihara ,  Masatsugu Akiyama ,  Kiyoshi Kawabata ,  Hisayoshi Yamanaka ,  Tetsuya Okishima

IPC分类号： H01L2338

CPC分类号： H01L24/49 ,  G11C5/04 ,  G11C5/06 ,  H01L23/50 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15183 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

摘要翻译： 一种具有布线基板，至少两个半导体芯片和总线的电子电路封装。 通过总线连接的所有半导体芯片都是裸线封装在布线基板上，并且半导体芯片和布线基板通过在半导体芯片上形成的引线键合焊盘和布线基板之间的布线接合来连接。 布线基板可以是多层基板。 优选地，在多层布线基板的表面上形成绝缘层和形成在绝缘层的表面上的管芯接合接地，以便在芯片接合地下使用多层布线基板的一部分作为布线 或通孔区域，并且在芯片接合地上形成至少一个半导体芯片。 总线优选地包括两条数据总线，与一条数据总线连接的半导体芯片形成在布线基板的一侧，并且在另一条数据总线上连接的半导体芯片形成在布线基板的另一侧。

公开(公告)号：US6101627A

公开(公告)日：2000-08-08

申请号：US206153

申请日：1998-12-07

申请人： Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

发明人： Tetsuya Shimomura ,  Fumio Murabayashi ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Takashi Hotta

IPC分类号： G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F11/30 ,  G06F13/00 ,  G06F15/78 ,  H02H3/05 ,  G06F7/02 ,  G06F11/08

CPC分类号： G06F11/1637 ,  G06F11/1654 ,  G06F11/2025 ,  G06F11/2038 ,  G06F11/2043

摘要： An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective ones result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

摘要翻译： 信息处理系统具有多个处理器电路，每个处理器电路包括内部电路和内部处理结果输出电路，该系统具有连接到每个处理器电路的内部数据选择电路和至少一个故障检测电路。 每个处理器电路的内部处理结果输出电路输出由处理器电路中的各个内部电路处理的各个结果数据。 每个内部数据选择电路在预定的定时选择并输出从每个处理器电路的内部处理结果输出电路输出的一个选择的结果数据。 故障检测电路输出由处理器电路的各个内部数据选择电路选择的数据或由处理器电路在每个预定定时输出的数据之间的比较结果。

公开(公告)号：US20140210393A1

公开(公告)日：2014-07-31

申请号：US14238054

申请日：2012-07-11

申请人： Nobuyasu Kanekawa ,  Ryoichi Kobayashi ,  Tomonobu Koseki ,  Chihiro Sato ,  Tomishige Yatsugi ,  Hirofumi Kurimoto

发明人： Nobuyasu Kanekawa ,  Ryoichi Kobayashi ,  Tomonobu Koseki ,  Chihiro Sato ,  Tomishige Yatsugi ,  Hirofumi Kurimoto

IPC分类号： H02J7/00 ,  B60R21/26 ,  H02P29/00

CPC分类号： H02J7/007 ,  B60R16/02 ,  B60R21/017 ,  H02M3/07 ,  H02P29/40 ,  H02P29/68 ,  Y10T307/461

摘要： A loss (generation of heat) is reduced in a capacitor precharge circuit, thereby reducing the size of the circuit.The capacitor precharge circuit according to the present invention divides a power supply voltage using a switched capacitor voltage divider circuit, thereby carrying out charging while suppressing a both-terminal voltage of the capacitor that is subject to the charging (refer to FIG. 1).

摘要翻译： 电容器预充电电路中的损耗（发热）降低，从而减小电路的尺寸。 根据本发明的电容器预充电电路使用开关电容器分压器电路分割电源电压，从而在抑制进行充电的电容器的两端电压（参照图1）的同时进行充电。

公开(公告)号：US08645022B2

公开(公告)日：2014-02-04

申请号：US12575212

申请日：2009-10-07

申请人： Kentaro Yoshimura ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Yuichiro Morita ,  Yoshiaki Takahashi ,  Kenichi Kurosawa ,  Toshimichi Minowa ,  Masatoshi Hoshino ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shoji Sasaki

发明人： Kentaro Yoshimura ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Yuichiro Morita ,  Yoshiaki Takahashi ,  Kenichi Kurosawa ,  Toshimichi Minowa ,  Masatoshi Hoshino ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shoji Sasaki

IPC分类号： G06F19/00 ,  G07C5/00

CPC分类号： B60W30/00 ,  B60K6/46 ,  B60K6/52 ,  B60L3/0023 ,  B60L3/003 ,  B60L3/0076 ,  B60L3/0092 ,  B60L15/2009 ,  B60L2240/12 ,  B60L2240/20 ,  B60L2240/24 ,  B60L2240/423 ,  B60L2250/26 ,  B60T7/12 ,  B60W10/04 ,  B60W10/06 ,  B60W10/08 ,  B60W10/10 ,  B60W10/18 ,  B60W10/20 ,  B60W20/00 ,  B60W40/08 ,  B60W40/10 ,  B60W50/02 ,  B60W50/0225 ,  B60W50/04 ,  B60W2510/20 ,  B60W2510/202 ,  B60W2520/14 ,  B60W2540/10 ,  B60W2540/12 ,  B60W2550/20 ,  B62D5/046 ,  B62D5/0481 ,  B62D6/00 ,  G06F11/0796 ,  Y02T10/6217 ,  Y02T10/6265 ,  Y02T10/6286 ,  Y02T10/645 ,  Y02T10/72 ,  Y02T10/7275 ,  Y02T90/16

摘要： A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network. The actuator controller includes a control target value generating unit for generating a control target value based on the sensor signals taken in by the sensor controller and received by the actuator controller via the network when the control target value generated by the command controller is abnormal, and controls the actuator in accordance with the control target value generated by the control target value generating unit.

摘要翻译： 一种车辆控制系统，可以通过简化的ECU配置和低成本确保高可靠性，实时处理和可扩展性，通过整个系统中的协调备份错误，而不会增加单个控制器的冗余程度，超出最不必要的范围 水平。 车辆控制系统包括：传感器控制器，用于接收指示车辆的状态变量的传感器信号和从驾驶员施加的操作量;命令控制器，用于基于由传感器控制器接收的传感器信号产生控制目标值; 以及致动器控制器，用于从命令控制器接收控制目标值并操作致动器来控制车辆，这三个控制器经由网络互连。 执行器控制器包括控制目标值产生单元，用于当由指令控制器产生的控制目标值异常时，基于由传感器控制器接收并由致动器控制器经由网络接收的传感器信号产生控制目标值;以及 根据由控制目标值产生单元产生的控制目标值来控制致动器。

公开(公告)号：US08639905B2

公开(公告)日：2014-01-28

申请号：US13614313

申请日：2012-09-13

申请人： Hiromichi Yamada ,  Yuichi Ishiguro ,  Nobuyasu Kanekawa

发明人： Hiromichi Yamada ,  Yuichi Ishiguro ,  Nobuyasu Kanekawa

IPC分类号： G06F12/02

CPC分类号： G06F11/1641 ,  G06F11/1683

摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

摘要翻译： 其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。 微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入 两次，并且第一次和第二次的写入数据被相互整理。

公开(公告)号：US20130105913A1

公开(公告)日：2013-05-02

申请号：US13807278

申请日：2011-06-02

申请人： Teppei Hirotsu ,  Nobuyasu Kanekawa ,  Itaru Tanabe

发明人： Teppei Hirotsu ,  Nobuyasu Kanekawa ,  Itaru Tanabe

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L27/0211 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/4238 ,  H03K17/145

摘要： This invention provides a current control semiconductor element in which dependence of a sense ratio on a temperature distribution is eliminated and the accuracy of current detection using a sense MOSFET can be improved, and to provide a control device using the current control semiconductor element. The current control semiconductor element 1 includes a main MOSFET 7 that drives a current and a sense MOSFET 8 that is connected to the main MOSFET in parallel and detects a current shunted from a current of the main MOSFET. The main MOSFET is formed using a multi-finger MOSFET that has a plurality of channels and is arranged in a row. When a distance between the center of the multi-finger MOSFET 7 and a channel located farthest from the center of the multi-finger MOSFET 7 is indicated by L, a channel that is located closest to a position distant by a distance of (L/(√3)) from the center of the multi-finger MOSFET is used as a channel for the sense MOSFET 8.

摘要翻译： 本发明提供了一种电流控制半导体元件，其中消除了感测比对温度分布的依赖性，并且可以提高使用感测MOSFET的电流检测的精度，并提供使用电流控制半导体元件的控制装置。 电流控制半导体元件1包括驱动电流的主MOSFET 7和并联连接到主MOSFET的感测MOSFET 8，并且检测从主MOSFET的电流分流的电流。 主MOSFET使用具有多个通道并排列成一排的多指MOSFET形成。 当多指MOSFET 7的中心与距离多指MOSFET 7的中心最远的通道之间的距离由L表示时，位于最靠近距离为（L / （√3））从多指MOSFET的中心用作感测MOSFET 8的通道。

公开(公告)号：US20130090813A1

公开(公告)日：2013-04-11

申请号：US13704864

申请日：2011-06-15

申请人： Nobuyasu Kanekawa ,  Ryoichi Kobayashi ,  Tomonobu Koseki ,  Keisuke Honda ,  Atsushi Uehara

发明人： Nobuyasu Kanekawa ,  Ryoichi Kobayashi ,  Tomonobu Koseki ,  Keisuke Honda ,  Atsushi Uehara

IPC分类号： B62D6/08 ,  H02J1/00

CPC分类号： B62D6/08 ,  B60R16/033 ,  B62D5/0481 ,  B62D5/0484 ,  H02J1/00 ,  Y02T10/92 ,  Y10T307/50 ,  Y10T307/685

摘要： An electronic control apparatus includes a control unit 2; a plurality of power supply units 1-1, 1-2 for supplying the control unit 2 with power; and a power supply fault detector unit 3 for detecting a fault in the plurality of power supply units 1-1, 1-2. The control unit 2 operates in a normal mode on electric power supplied from the plurality of power supply units 1-1, 1-2, when none of the plurality of power supply units 1-1, 1-2 is faulty. If at least one of the plurality of power supply units 1-1, 1-2 is faulty, the control unit 2 operates in an energy saving mode in which less power is consumed on electric power supplied from the power supply unit that remains fully operational. Thereby an electronic control apparatus is obtained that enables continued operation during a faulty condition, while preventing circuit scale, dimensions, weight, and cost from increasing.

摘要翻译： 电子控制装置包括控制单元2; 用于向控制单元2供电的多个电源单元1-1,1-2; 以及用于检测多个电源单元1-1,1-2中的故障的电源故障检测器单元3。 当多个电源单元1-1,1-2中没有一个发生故障时，控制单元2以正常模式操作从多个电源单元1-1,1-2提供的电力。 如果多个电源单元1-1,1-2中的至少一个出现故障，则控制单元2以节能模式工作，其中从供电单元供电的电力消耗的功率较少，该功率保持完全可操作 。 从而获得能够在故障状态下继续运转的电子控制装置，同时防止电路规模，尺寸，重量和成本增加。

公开(公告)号：US07836233B2

公开(公告)日：2010-11-16

申请号：US10642755

申请日：2003-08-19

申请人： Kunihiko Tsunedomi ,  Kentaro Yoshimura ,  Nobuyasu Kanekawa ,  Takanori Yokoyama ,  Mitsuru Watabe

发明人： Kunihiko Tsunedomi ,  Kentaro Yoshimura ,  Nobuyasu Kanekawa ,  Takanori Yokoyama ,  Mitsuru Watabe

IPC分类号： G06F13/00

CPC分类号： G05B19/0421 ,  G05B2219/2231 ,  G05B2219/25178

摘要： A serial communication interface (SCI) cable 4 is provided between the slave processor 2 and the master processor 3. Both processors are connected with a communication interface for peripheral units (SPI: Serial Peripheral Interface) which enables fast transmission. The slave processor 2 transmits a transmission request command which requests at least one of data transmission and reception from the command communication section 220 to the master processor 3 through the SCI cable 4. The master processor 3 transfers data to and from the slave processor 2 in communication with the slave processor 2 by means of the data communication section 310 through the fast SPI cable 5 in response to a transmission request command sent from the slave processor 2 With this, the processing ability of a multi-processor system can be increased.

摘要翻译： 在从属处理器2和主处理器3之间提供串行通信接口（SCI）电缆4.两个处理器都连接有外围设备的通信接口（SPI：串行外设接口），可实现快速传输。 从处理器2通过SCI电缆4发送从命令通信部220向主处理器3请求数据发送和接收中的至少一个的发送请求命令。主处理器3将来自从处理器2的数据传送到从处理器2 响应于从从属处理器2发送的发送请求命令，通过数据通信部分310通过快速SPI电缆5与从属处理器2进行通信。由此，可以增加多处理器系统的处理能力。