公开(公告)号：US20170236941A1

公开(公告)日：2017-08-17

申请号：US15583011

申请日：2017-05-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Yutaka OKAZAKI

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696

Abstract: To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor device, an oxide semiconductor layer is surrounded by an insulating layer including an aluminum oxide film containing excess oxygen. Excess oxygen in the aluminum oxide film is supplied to the oxide semiconductor layer including a channel by heat treatment in a manufacturing process of the semiconductor device. Furthermore, the aluminum oxide film forms a barrier against oxygen and hydrogen. It is thus possible to suppress the removal of oxygen from the oxide semiconductor layer surrounded by the insulating layer including an aluminum oxide film, and the entry of impurities such as hydrogen into the oxide semiconductor layer; as a result, the oxide semiconductor layer can be made highly intrinsic. In addition, gate electrode layers over and under the oxide semiconductor layer control the threshold voltage effectively.

公开(公告)号：US20170207347A1

公开(公告)日：2017-07-20

申请号：US15408719

申请日：2017-01-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Satoru OKAMOTO

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/146 ,  H01L29/49 ,  H01L27/12 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/401 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78693 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

公开(公告)号：US20160343870A1

公开(公告)日：2016-11-24

申请号：US15230732

申请日：2016-08-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/792 ,  H01L21/441 ,  H01L29/51 ,  H01L29/49 ,  H01L21/465 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31645 ,  H01L21/32136 ,  H01L21/441 ,  H01L21/465 ,  H01L21/473 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696 ,  H01L29/792

Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

公开(公告)号：US20160247832A1

公开(公告)日：2016-08-25

申请号：US15041502

申请日：2016-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Yuta ENDO ,  Kazuya HANAOKA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/475 ,  H01L21/47573 ,  H01L27/1207 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.

Abstract translation: 提供具有降低的寄生电容的半导体器件。 半导体器件包括第一绝缘层; 第一绝缘层上的第一氧化物层; 在所述第一氧化物层上的半导体层; 半导体层上的源电极层和漏电极层; 在所述第一绝缘层上的第二绝缘层; 在第二绝缘层上的第三绝缘层，源电极层和漏电极层; 半导体层上的第二氧化物层; 第二氧化物层上的栅极绝缘层; 栅绝缘层上的栅电极层; 以及第三绝缘层，第二氧化物层，栅极绝缘层和栅极电极层上的第四绝缘层。

公开(公告)号：US20160190273A1

公开(公告)日：2016-06-30

申请号：US15066018

申请日：2016-03-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Hiroshi FUJIKI ,  Hiromichi GODO ,  Yasumasa YAMANE

IPC: H01L29/49 ,  H01L29/786 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/4908 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/45 ,  H01L29/7869

Abstract: The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced.

Abstract translation: 通过尽可能地抑制晶体管的电特性的变化来提高半导体器件的可靠性。 作为包括氧化物半导体的晶体管的电特性变化的原因，可以给出氧化物半导体中的氢浓度，氧化物半导体中的氧空位密度等。 源电极和漏电极使用容易与氧结合的导电材料形成。 使用在含有氧的气氛下通过溅射法等形成的氧化物层形成沟道形成区域。 因此，可以降低堆叠中的氢浓度，特别是可以降低通道形成区域中的氢浓度。

公开(公告)号：US20160163744A1

公开(公告)日：2016-06-09

申请号：US15041338

申请日：2016-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02609 ,  H01L21/02617 ,  H01L21/02631 ,  H01L29/045 ,  H01L29/26 ,  H01L29/78 ,  H01L29/7869

Abstract: A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for metal films of a source electrode layer, a drain electrode layer, and a gate electrode layer, whereby diffusion of oxygen to the metal films is suppressed.

Abstract translation: 提供了可以抑制氧化物半导体层中氧空位增加的半导体器件。 提供了具有良好电气特性的半导体器件。 提供了一种高度可靠的半导体器件。 半导体器件包括在沟道形成区域中的氧化物半导体层，并且通过使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触的栅绝缘膜， 氧化物绝缘膜或栅极绝缘膜被提供给氧化物半导体层。 此外，导电氮化物用于源电极层，漏电极层和栅电极层的金属膜，由此抑制氧向金属膜的扩散。

公开(公告)号：US20160111546A1

公开(公告)日：2016-04-21

申请号：US14883732

申请日：2015-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki TEZUKA ,  Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Hideomi SUZAWA ,  Suguru HONDO

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78

Abstract: Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.

Abstract translation: 为包括氧化物半导体的小型半导体器件提供稳定的电特性和高可靠性，并且制造半导体器件。 半导体器件包括基极绝缘层; 氧化物堆叠，其在所述基底绝缘层上方并且包括氧化物半导体层; 氧化层上的源电极层和漏电极层; 氧化层上的栅极绝缘层，源电极层和漏电极层; 栅绝缘层上的栅电极层; 以及在栅电极层上的层间绝缘层。 在半导体器件中，氧化物半导体层中的缺陷密度降低。

公开(公告)号：US20160099261A1

公开(公告)日：2016-04-07

申请号：US14873863

申请日：2015-10-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji Ono ,  Hideomi SUZAWA

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/1214 ,  C23F4/00 ,  H01B1/02 ,  H01B5/14 ,  H01B13/0006 ,  H01B13/0036 ,  H01L21/32136 ,  H01L21/76838 ,  H01L27/12 ,  H01L27/124 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/495 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.

Abstract translation: 提供适合于大尺寸基板的金属布线。 本发明的特征在于，在绝缘表面上形成至少一层导电膜，在导电膜上形成抗蚀剂图案，并且蚀刻具有抗蚀剂图案的导电膜以形成金属布线，同时控制其锥度 根据偏置功率密度，ICP功率密度，下部电极的温度，压力，蚀刻气体的总流量，或蚀刻气体中的氧气或氯气的比例来确定角度α。 这样形成的金属布线的宽度或长度波动较小，并且可以令人满意地处理基板尺寸的增加。

公开(公告)号：US20150228802A1

公开(公告)日：2015-08-13

申请号：US14696841

申请日：2015-04-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA

IPC: H01L29/786 ,  H01L29/51

CPC classification number: H01L29/7869 ,  H01L29/4908 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78621

Abstract: An object is to provide a transistor including an oxide semiconductor having favorable electrical characteristics and a manufacturing method thereof. A semiconductor device includes an oxide semiconductor film and an insulating film over a substrate. An end portion of the oxide semiconductor film is in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. The semiconductor device further includes a gate insulating film over and in contact with the oxide semiconductor film, a gate electrode with a sidewall insulating film over the gate insulating film, and a source electrode and a drain electrode in contact with the sidewall insulating film, the oxide semiconductor film, and the insulating film.

Abstract translation: 目的在于提供一种具有良好的电气特性的氧化物半导体的晶体管及其制造方法。 半导体器件包括氧化物半导体膜和衬底上的绝缘膜。 氧化物半导体膜的端部与绝缘膜接触。 氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。 半导体器件还包括在氧化物半导体膜上并与之接触的栅极绝缘膜，在栅极绝缘膜上具有侧壁绝缘膜的栅电极以及与侧壁绝缘膜接触的源电极和漏电极， 氧化物半导体膜和绝缘膜。

公开(公告)号：US20150037932A1

公开(公告)日：2015-02-05

申请号：US14459597

申请日：2014-08-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02488 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

Abstract translation: 提供了包括氧化物半导体并且具有良好的电特性的半导体器件。 在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。 氧化物半导体膜的侧面与绝缘膜接触。 氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。 栅极绝缘膜与氧化物半导体膜形成并接触。 在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。 源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。